[PATCH] D122052: [RISCV] Add test case for miscompile caused by treating ANY_EXTEND of constants as SIGN_EXTEND.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 18 18:24:36 PDT 2022
craig.topper created this revision.
craig.topper added reviewers: jrtc27, asb, frasercrmck, luismarques.
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Herald added a project: LLVM.
The code that inserts AssertZExt based on predecessor information assumes
constants are zero extended for phi incoming values this allows
AssertZExt to be created in blocks consuming a Phi.
SelectionDAG::getNode treats any_extend of i32 constants as sext for RISCV.
The code that creates phi incoming values in the predecessors creates an
any_extend for the constants which then gets treated as a sext by getNode.
This makes the AssertZExt incorrect and can cause zexts to be
incorrectly removed.
This bug was introduced by D105918 <https://reviews.llvm.org/D105918>
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D122052
Files:
llvm/test/CodeGen/RISCV/aext-to-sext.ll
Index: llvm/test/CodeGen/RISCV/aext-to-sext.ll
===================================================================
--- llvm/test/CodeGen/RISCV/aext-to-sext.ll
+++ llvm/test/CodeGen/RISCV/aext-to-sext.ll
@@ -75,3 +75,36 @@
bar:
ret i32 %b
}
+
+; The code that inserts AssertZExt based on predecessor information assumes
+; constants are zero extended for phi incoming values so an AssertZExt is
+; created in 'merge' allowing the zext to be removed.
+; SelectionDAG::getNode treats any_extend of i32 constants as sext for RISCV.
+; The code that creates phi incoming values in the predecessors creates an
+; any_extend for the constants which then gets treated as a sext by getNode.
+; This means the zext was not safe to remove.
+define i64 @miscompile(i32 %c) {
+; RV64I-LABEL: miscompile:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sext.w a1, a0
+; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: beqz a1, .LBB2_2
+; RV64I-NEXT: # %bb.1: # %merge
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB2_2: # %iffalse
+; RV64I-NEXT: li a0, -2
+; RV64I-NEXT: ret
+ %a = icmp ne i32 %c, 0
+ br i1 %a, label %iftrue, label %iffalse
+
+iftrue:
+ br label %merge
+
+iffalse:
+ br label %merge
+
+merge:
+ %b = phi i32 [-1, %iftrue], [-2, %iffalse]
+ %d = zext i32 %b to i64
+ ret i64 %d
+}
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