[PATCH] D122051: [RISCV] The immediate version of sgt lowering to slti + xori

[LiqinWeng via Phabricator via llvm-commits]

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li   a1, 5  slt     a0, a1, a0 ------> slti    a0, a0, 6  xori    a0, a0, 1 , which can reduce the number of registers used


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D122051

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/i32-icmp.ll

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