[llvm] 3abf8eb - [slp][tests] Add missing function attributes
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 18 15:52:09 PDT 2022
Author: Philip Reames
Date: 2022-03-18T15:51:42-07:00
New Revision: 3abf8ebd9a7522b6d81f761aa3d57202fe2425bf
URL: https://github.com/llvm/llvm-project/commit/3abf8ebd9a7522b6d81f761aa3d57202fe2425bf
DIFF: https://github.com/llvm/llvm-project/commit/3abf8ebd9a7522b6d81f761aa3d57202fe2425bf.diff
LOG: [slp][tests] Add missing function attributes
SLP is currently assuming that control dependence in these cases is irrelevant. This is only valid if none of the lib-funcs involved can throw or infinite loop in the scalar forms. This appears to be true (or at least we infer the respective attributes) for the libfuncs I spot checked. This change is mostly for shrunking the diff on an upcoming patch.
Added:
Modified:
llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
llvm/test/Transforms/SLPVectorizer/X86/call.ll
llvm/test/Transforms/SLPVectorizer/X86/funclet.ll
llvm/test/Transforms/SLPVectorizer/vectorizable-functions-inseltpoison.ll
llvm/test/Transforms/SLPVectorizer/vectorizable-functions.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
index f99f81b42fe8f..fcc70d9e6af7f 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
@@ -50,7 +50,7 @@ entry:
ret <4 x float> %vecins.3
}
-declare float @ceilf(float) readonly
+declare float @ceilf(float) readonly nounwind willreturn
define <4 x float> @ceil_4x(<4 x float>* %a) {
; CHECK-LABEL: @ceil_4x(
@@ -82,7 +82,7 @@ entry:
ret <4 x float> %vecins.3
}
-declare float @fabsf(float) readonly
+declare float @fabsf(float) readonly nounwind willreturn
define <4 x float> @fabs_4x(<4 x float>* %a) {
; CHECK-LABEL: @fabs_4x(
@@ -113,7 +113,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @llvm.fabs.f32(float)
+declare float @llvm.fabs.f32(float) nounwind willreturn
define <4 x float> @int_fabs_4x(<4 x float>* %a) {
; CHECK-LABEL: @int_fabs_4x(
; CHECK-NEXT: entry:
@@ -143,7 +143,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @floorf(float) readonly
+declare float @floorf(float) readonly nounwind willreturn
define <4 x float> @floor_4x(<4 x float>* %a) {
; CHECK-LABEL: @floor_4x(
; CHECK-NEXT: entry:
@@ -173,7 +173,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @sqrtf(float) readonly
+declare float @sqrtf(float) readonly nounwind willreturn
define <4 x float> @sqrt_4x(<4 x float>* %a) {
; CHECK-LABEL: @sqrt_4x(
; CHECK-NEXT: entry:
@@ -203,7 +203,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @expf(float) readonly
+declare float @expf(float) readonly nounwind willreturn
define <4 x float> @exp_4x(<4 x float>* %a) {
; CHECK-LABEL: @exp_4x(
; CHECK-NEXT: entry:
@@ -245,7 +245,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @expm1f(float) readonly
+declare float @expm1f(float) readonly nounwind willreturn
define <4 x float> @expm1_4x(<4 x float>* %a) {
; CHECK-LABEL: @expm1_4x(
; CHECK-NEXT: entry:
@@ -286,7 +286,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @logf(float) readonly
+declare float @logf(float) readonly nounwind willreturn
define <4 x float> @log_4x(<4 x float>* %a) {
; CHECK-LABEL: @log_4x(
; CHECK-NEXT: entry:
@@ -328,7 +328,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @log1pf(float) readonly
+declare float @log1pf(float) readonly nounwind willreturn
define <4 x float> @log1p_4x(<4 x float>* %a) {
; CHECK-LABEL: @log1p_4x(
; CHECK-NEXT: entry:
@@ -369,7 +369,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @log10pf(float) readonly
+declare float @log10pf(float) readonly nounwind willreturn
define <4 x float> @log10p_4x(<4 x float>* %a) {
; CHECK-LABEL: @log10p_4x(
; CHECK-NEXT: entry:
@@ -421,7 +421,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @logbf(float) readonly
+declare float @logbf(float) readonly nounwind willreturn
define <4 x float> @logb_4x(<4 x float>* %a) {
; CHECK-LABEL: @logb_4x(
; CHECK-NEXT: entry:
@@ -462,7 +462,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @sinf(float) readonly
+declare float @sinf(float) readonly nounwind willreturn
define <4 x float> @sin_4x(<4 x float>* %a) {
; CHECK-LABEL: @sin_4x(
; CHECK-NEXT: entry:
@@ -504,7 +504,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @cosf(float) readonly
+declare float @cosf(float) readonly nounwind willreturn
define <4 x float> @cos_4x(<4 x float>* %a) {
; CHECK-LABEL: @cos_4x(
; CHECK-NEXT: entry:
@@ -546,7 +546,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @tanf(float) readonly
+declare float @tanf(float) readonly nounwind willreturn
define <4 x float> @tan_4x(<4 x float>* %a) {
; CHECK-LABEL: @tan_4x(
; CHECK-NEXT: entry:
@@ -587,7 +587,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @asinf(float) readonly
+declare float @asinf(float) readonly nounwind willreturn
define <4 x float> @asin_4x(<4 x float>* %a) {
; CHECK-LABEL: @asin_4x(
; CHECK-NEXT: entry:
@@ -628,7 +628,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @acosf(float) readonly
+declare float @acosf(float) readonly nounwind willreturn
define <4 x float> @acos_4x(<4 x float>* %a) {
; CHECK-LABEL: @acos_4x(
; CHECK-NEXT: entry:
@@ -669,7 +669,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @atanf(float) readonly
+declare float @atanf(float) readonly nounwind willreturn
define <4 x float> @atan_4x(<4 x float>* %a) {
; CHECK-LABEL: @atan_4x(
; CHECK-NEXT: entry:
@@ -710,7 +710,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @sinhf(float) readonly
+declare float @sinhf(float) readonly nounwind willreturn
define <4 x float> @sinh_4x(<4 x float>* %a) {
; CHECK-LABEL: @sinh_4x(
; CHECK-NEXT: entry:
@@ -751,7 +751,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @coshf(float) readonly
+declare float @coshf(float) readonly nounwind willreturn
define <4 x float> @cosh_4x(<4 x float>* %a) {
; CHECK-LABEL: @cosh_4x(
; CHECK-NEXT: entry:
@@ -792,7 +792,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @tanhf(float) readonly
+declare float @tanhf(float) readonly nounwind willreturn
define <4 x float> @tanh_4x(<4 x float>* %a) {
; CHECK-LABEL: @tanh_4x(
; CHECK-NEXT: entry:
@@ -833,7 +833,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @asinhf(float) readonly
+declare float @asinhf(float) readonly nounwind willreturn
define <4 x float> @asinh_4x(<4 x float>* %a) {
; CHECK-LABEL: @asinh_4x(
; CHECK-NEXT: entry:
@@ -874,7 +874,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @acoshf(float) readonly
+declare float @acoshf(float) readonly nounwind willreturn
define <4 x float> @acosh_4x(<4 x float>* %a) {
; CHECK-LABEL: @acosh_4x(
; CHECK-NEXT: entry:
@@ -915,7 +915,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @atanhf(float) readonly
+declare float @atanhf(float) readonly nounwind willreturn
define <4 x float> @atanh_4x(<4 x float>* %a) {
; CHECK-LABEL: @atanh_4x(
; CHECK-NEXT: entry:
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
index 454321423236f..77def6ae2db31 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
@@ -50,7 +50,7 @@ entry:
ret <4 x float> %vecins.3
}
-declare float @ceilf(float) readonly
+declare float @ceilf(float) readonly nounwind willreturn
define <4 x float> @ceil_4x(<4 x float>* %a) {
; CHECK-LABEL: @ceil_4x(
@@ -82,7 +82,7 @@ entry:
ret <4 x float> %vecins.3
}
-declare float @fabsf(float) readonly
+declare float @fabsf(float) readonly nounwind willreturn
define <4 x float> @fabs_4x(<4 x float>* %a) {
; CHECK-LABEL: @fabs_4x(
@@ -143,7 +143,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @floorf(float) readonly
+declare float @floorf(float) readonly nounwind willreturn
define <4 x float> @floor_4x(<4 x float>* %a) {
; CHECK-LABEL: @floor_4x(
; CHECK-NEXT: entry:
@@ -173,7 +173,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @sqrtf(float) readonly
+declare float @sqrtf(float) readonly nounwind willreturn
define <4 x float> @sqrt_4x(<4 x float>* %a) {
; CHECK-LABEL: @sqrt_4x(
; CHECK-NEXT: entry:
@@ -203,7 +203,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @expf(float) readonly
+declare float @expf(float) readonly nounwind willreturn
define <4 x float> @exp_4x(<4 x float>* %a) {
; CHECK-LABEL: @exp_4x(
; CHECK-NEXT: entry:
@@ -245,7 +245,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @expm1f(float) readonly
+declare float @expm1f(float) readonly nounwind willreturn
define <4 x float> @expm1_4x(<4 x float>* %a) {
; CHECK-LABEL: @expm1_4x(
; CHECK-NEXT: entry:
@@ -286,7 +286,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @logf(float) readonly
+declare float @logf(float) readonly nounwind willreturn
define <4 x float> @log_4x(<4 x float>* %a) {
; CHECK-LABEL: @log_4x(
; CHECK-NEXT: entry:
@@ -328,7 +328,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @log1pf(float) readonly
+declare float @log1pf(float) readonly nounwind willreturn
define <4 x float> @log1p_4x(<4 x float>* %a) {
; CHECK-LABEL: @log1p_4x(
; CHECK-NEXT: entry:
@@ -369,7 +369,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @log10pf(float) readonly
+declare float @log10pf(float) readonly nounwind willreturn
define <4 x float> @log10p_4x(<4 x float>* %a) {
; CHECK-LABEL: @log10p_4x(
; CHECK-NEXT: entry:
@@ -421,7 +421,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @logbf(float) readonly
+declare float @logbf(float) readonly nounwind willreturn
define <4 x float> @logb_4x(<4 x float>* %a) {
; CHECK-LABEL: @logb_4x(
; CHECK-NEXT: entry:
@@ -462,7 +462,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @sinf(float) readonly
+declare float @sinf(float) readonly nounwind willreturn
define <4 x float> @sin_4x(<4 x float>* %a) {
; CHECK-LABEL: @sin_4x(
; CHECK-NEXT: entry:
@@ -504,7 +504,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @cosf(float) readonly
+declare float @cosf(float) readonly nounwind willreturn
define <4 x float> @cos_4x(<4 x float>* %a) {
; CHECK-LABEL: @cos_4x(
; CHECK-NEXT: entry:
@@ -546,7 +546,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @tanf(float) readonly
+declare float @tanf(float) readonly nounwind willreturn
define <4 x float> @tan_4x(<4 x float>* %a) {
; CHECK-LABEL: @tan_4x(
; CHECK-NEXT: entry:
@@ -587,7 +587,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @asinf(float) readonly
+declare float @asinf(float) readonly nounwind willreturn
define <4 x float> @asin_4x(<4 x float>* %a) {
; CHECK-LABEL: @asin_4x(
; CHECK-NEXT: entry:
@@ -628,7 +628,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @acosf(float) readonly
+declare float @acosf(float) readonly nounwind willreturn
define <4 x float> @acos_4x(<4 x float>* %a) {
; CHECK-LABEL: @acos_4x(
; CHECK-NEXT: entry:
@@ -669,7 +669,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @atanf(float) readonly
+declare float @atanf(float) readonly nounwind willreturn
define <4 x float> @atan_4x(<4 x float>* %a) {
; CHECK-LABEL: @atan_4x(
; CHECK-NEXT: entry:
@@ -710,7 +710,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @sinhf(float) readonly
+declare float @sinhf(float) readonly nounwind willreturn
define <4 x float> @sinh_4x(<4 x float>* %a) {
; CHECK-LABEL: @sinh_4x(
; CHECK-NEXT: entry:
@@ -751,7 +751,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @coshf(float) readonly
+declare float @coshf(float) readonly nounwind willreturn
define <4 x float> @cosh_4x(<4 x float>* %a) {
; CHECK-LABEL: @cosh_4x(
; CHECK-NEXT: entry:
@@ -792,7 +792,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @tanhf(float) readonly
+declare float @tanhf(float) readonly nounwind willreturn
define <4 x float> @tanh_4x(<4 x float>* %a) {
; CHECK-LABEL: @tanh_4x(
; CHECK-NEXT: entry:
@@ -833,7 +833,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @asinhf(float) readonly
+declare float @asinhf(float) readonly nounwind willreturn
define <4 x float> @asinh_4x(<4 x float>* %a) {
; CHECK-LABEL: @asinh_4x(
; CHECK-NEXT: entry:
@@ -874,7 +874,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @acoshf(float) readonly
+declare float @acoshf(float) readonly nounwind willreturn
define <4 x float> @acosh_4x(<4 x float>* %a) {
; CHECK-LABEL: @acosh_4x(
; CHECK-NEXT: entry:
@@ -915,7 +915,7 @@ entry:
%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
ret <4 x float> %vecins.3
}
-declare float @atanhf(float) readonly
+declare float @atanhf(float) readonly nounwind willreturn
define <4 x float> @atanh_4x(<4 x float>* %a) {
; CHECK-LABEL: @atanh_4x(
; CHECK-NEXT: entry:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/call.ll b/llvm/test/Transforms/SLPVectorizer/X86/call.ll
index a0dece0a58b47..29cd5b2a13250 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/call.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/call.ll
@@ -4,12 +4,12 @@
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.8.0"
-declare double @sin(double)
-declare double @cos(double)
-declare double @pow(double, double)
-declare double @exp2(double)
-declare double @sqrt(double)
-declare i64 @round(i64)
+declare double @sin(double) nounwind willreturn
+declare double @cos(double) nounwind willreturn
+declare double @pow(double, double) nounwind willreturn
+declare double @exp2(double) nounwind willreturn
+declare double @sqrt(double) nounwind willreturn
+declare i64 @round(i64) nounwind willreturn
define void @sin_libm(double* %a, double* %b) {
@@ -125,8 +125,8 @@ define void @sqrt_libm_errno(double* %a, double* %b) {
; CHECK-NEXT: [[A0:%.*]] = load double, double* [[A:%.*]], align 8
; CHECK-NEXT: [[IDX1:%.*]] = getelementptr inbounds double, double* [[A]], i64 1
; CHECK-NEXT: [[A1:%.*]] = load double, double* [[IDX1]], align 8
-; CHECK-NEXT: [[SQRT1:%.*]] = tail call nnan double @sqrt(double [[A0]]) #[[ATTR2:[0-9]+]]
-; CHECK-NEXT: [[SQRT2:%.*]] = tail call nnan double @sqrt(double [[A1]]) #[[ATTR2]]
+; CHECK-NEXT: [[SQRT1:%.*]] = tail call nnan double @sqrt(double [[A0]]) #[[ATTR3:[0-9]+]]
+; CHECK-NEXT: [[SQRT2:%.*]] = tail call nnan double @sqrt(double [[A1]]) #[[ATTR3]]
; CHECK-NEXT: store double [[SQRT1]], double* [[B:%.*]], align 8
; CHECK-NEXT: [[IDX2:%.*]] = getelementptr inbounds double, double* [[B]], i64 1
; CHECK-NEXT: store double [[SQRT2]], double* [[IDX2]], align 8
@@ -149,8 +149,8 @@ define void @round_custom(i64* %a, i64* %b) {
; CHECK-NEXT: [[A0:%.*]] = load i64, i64* [[A:%.*]], align 8
; CHECK-NEXT: [[IDX1:%.*]] = getelementptr inbounds i64, i64* [[A]], i64 1
; CHECK-NEXT: [[A1:%.*]] = load i64, i64* [[IDX1]], align 8
-; CHECK-NEXT: [[ROUND1:%.*]] = tail call i64 @round(i64 [[A0]]) #[[ATTR3:[0-9]+]]
-; CHECK-NEXT: [[ROUND2:%.*]] = tail call i64 @round(i64 [[A1]]) #[[ATTR3]]
+; CHECK-NEXT: [[ROUND1:%.*]] = tail call i64 @round(i64 [[A0]]) #[[ATTR4:[0-9]+]]
+; CHECK-NEXT: [[ROUND2:%.*]] = tail call i64 @round(i64 [[A1]]) #[[ATTR4]]
; CHECK-NEXT: store i64 [[ROUND1]], i64* [[B:%.*]], align 8
; CHECK-NEXT: [[IDX2:%.*]] = getelementptr inbounds i64, i64* [[B]], i64 1
; CHECK-NEXT: store i64 [[ROUND2]], i64* [[IDX2]], align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/funclet.ll b/llvm/test/Transforms/SLPVectorizer/X86/funclet.ll
index ae24e92d9e515..7198279eea2d4 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/funclet.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/funclet.ll
@@ -67,4 +67,4 @@ declare i32 @__CxxFrameHandler3(...)
declare double @floor(double) #1
attributes #0 = { "target-features"="+sse2" }
-attributes #1 = { nounwind readnone }
+attributes #1 = { nounwind readnone willreturn }
diff --git a/llvm/test/Transforms/SLPVectorizer/vectorizable-functions-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/vectorizable-functions-inseltpoison.ll
index 740639a8ec555..73cc950cc1390 100644
--- a/llvm/test/Transforms/SLPVectorizer/vectorizable-functions-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/vectorizable-functions-inseltpoison.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -slp-vectorizer -S %s | FileCheck %s
-declare float @memread(float) readonly #0
+declare float @memread(float) readonly nounwind willreturn #0
declare <4 x float> @vmemread(<4 x float>)
define <4 x float> @memread_4x(<4 x float>* %a) {
@@ -28,7 +28,7 @@ entry:
ret <4 x float> %vecins.3
}
-declare float @memwrite(float) #1
+declare float @memwrite(float) nounwind willreturn #1
declare <4 x float> @vmemwrite(<4 x float>)
define <4 x float> @memwrite_4x(<4 x float>* %a) {
@@ -36,16 +36,16 @@ define <4 x float> @memwrite_4x(<4 x float>* %a) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = tail call fast float @memwrite(float [[VECEXT]]) #[[ATTR1:[0-9]+]]
+; CHECK-NEXT: [[TMP1:%.*]] = tail call fast float @memwrite(float [[VECEXT]]) #[[ATTR2:[0-9]+]]
; CHECK-NEXT: [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
; CHECK-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = tail call fast float @memwrite(float [[VECEXT_1]]) #[[ATTR1]]
+; CHECK-NEXT: [[TMP2:%.*]] = tail call fast float @memwrite(float [[VECEXT_1]]) #[[ATTR2]]
; CHECK-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
; CHECK-NEXT: [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = tail call fast float @memwrite(float [[VECEXT_2]]) #[[ATTR1]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call fast float @memwrite(float [[VECEXT_2]]) #[[ATTR2]]
; CHECK-NEXT: [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
; CHECK-NEXT: [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
-; CHECK-NEXT: [[TMP4:%.*]] = tail call fast float @memwrite(float [[VECEXT_3]]) #[[ATTR1]]
+; CHECK-NEXT: [[TMP4:%.*]] = tail call fast float @memwrite(float [[VECEXT_3]]) #[[ATTR2]]
; CHECK-NEXT: [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
; CHECK-NEXT: ret <4 x float> [[VECINS_3]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/vectorizable-functions.ll b/llvm/test/Transforms/SLPVectorizer/vectorizable-functions.ll
index 51fce1134dc32..20af1b7c507e4 100644
--- a/llvm/test/Transforms/SLPVectorizer/vectorizable-functions.ll
+++ b/llvm/test/Transforms/SLPVectorizer/vectorizable-functions.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -slp-vectorizer -S %s | FileCheck %s
-declare float @memread(float) readonly #0
+declare float @memread(float) readonly nounwind willreturn #0
declare <4 x float> @vmemread(<4 x float>)
define <4 x float> @memread_4x(<4 x float>* %a) {
@@ -28,7 +28,7 @@ entry:
ret <4 x float> %vecins.3
}
-declare float @memwrite(float) #1
+declare float @memwrite(float) nounwind willreturn #1
declare <4 x float> @vmemwrite(<4 x float>)
define <4 x float> @memwrite_4x(<4 x float>* %a) {
@@ -36,16 +36,16 @@ define <4 x float> @memwrite_4x(<4 x float>* %a) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = tail call fast float @memwrite(float [[VECEXT]]) #[[ATTR1:[0-9]+]]
+; CHECK-NEXT: [[TMP1:%.*]] = tail call fast float @memwrite(float [[VECEXT]]) #[[ATTR2:[0-9]+]]
; CHECK-NEXT: [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0
; CHECK-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = tail call fast float @memwrite(float [[VECEXT_1]]) #[[ATTR1]]
+; CHECK-NEXT: [[TMP2:%.*]] = tail call fast float @memwrite(float [[VECEXT_1]]) #[[ATTR2]]
; CHECK-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
; CHECK-NEXT: [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = tail call fast float @memwrite(float [[VECEXT_2]]) #[[ATTR1]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call fast float @memwrite(float [[VECEXT_2]]) #[[ATTR2]]
; CHECK-NEXT: [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
; CHECK-NEXT: [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
-; CHECK-NEXT: [[TMP4:%.*]] = tail call fast float @memwrite(float [[VECEXT_3]]) #[[ATTR1]]
+; CHECK-NEXT: [[TMP4:%.*]] = tail call fast float @memwrite(float [[VECEXT_3]]) #[[ATTR2]]
; CHECK-NEXT: [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
; CHECK-NEXT: ret <4 x float> [[VECINS_3]]
;
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