[PATCH] D121524: [AMDGPU] use scalar shift for SALU users in frame index elimination

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:2237
+        bool IsSALU = isSGPRClass(TII->getOpRegClass(*MI, FIOperandNum));
+        bool LiveSCC = RS->isRegUsed(AMDGPU::SCC);
+        const TargetRegisterClass *RC = IsSALU && !LiveSCC
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rampitec wrote:
> alex-t wrote:
> > rampitec wrote:
> > > alex-t wrote:
> > > > rampitec wrote:
> > > > > Is not isRegUsed for the whole function and will always return true on practice?
> > > > This function is used to determine if SCC is live in all other places around the code.
> > > > Another option is to scan upwards until the block start is reached.
> > > All other places shall mean the whole function? I'd suggest using MBB->computeRegisterLiveness().
> > I mean checks like this:
> > 
> > CanClobberSCC = !RS->isRegUsed(AMDGPU::SCC);
> > 
> > they really interested if SCC is live at exact point.
> > 
> > In case this is wrong we have lots of problems
> But what point is it? The call does not take an iterator.
It's at the scavenging point, which is separately advanced


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  https://reviews.llvm.org/D121524/new/

https://reviews.llvm.org/D121524