[PATCH] D121887: [RISCV] Teach VSETVLI insertion that it doesn't need to insert vsetvli for vlm.v and vsm.v in some cases.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

vlm and vsm instructions should be created with an SEW of 0 so they should be treated as `MaskRegOp` by the vsetvli pass.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121887/new/

https://reviews.llvm.org/D121887