[PATCH] D121887: [RISCV] Teach VSETVLI insertion that it doesn't need to insert vsetvli for vlm.v and vsm.v in some cases.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 17 13:16:13 PDT 2022
craig.topper added a comment.
vlm and vsm instructions should be created with an SEW of 0 so they should be treated as `MaskRegOp` by the vsetvli pass.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D121887/new/
https://reviews.llvm.org/D121887
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