[PATCH] D121645: [RISCV] Simplify scalable vector case in lowerVectorMaskExt.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 17 09:43:47 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7e15303062b5: [RISCV] Simplify scalable vector case in lowerVectorMaskExt. (authored by craig.topper).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D121645/new/
https://reviews.llvm.org/D121645
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4267,30 +4267,9 @@
assert(Src.getValueType().isVector() &&
Src.getValueType().getVectorElementType() == MVT::i1);
- MVT XLenVT = Subtarget.getXLenVT();
- SDValue SplatZero = DAG.getConstant(0, DL, XLenVT);
- SDValue SplatTrueVal = DAG.getConstant(ExtTrueVal, DL, XLenVT);
-
if (VecVT.isScalableVector()) {
- // Be careful not to introduce illegal scalar types at this stage, and be
- // careful also about splatting constants as on RV32, vXi64 SPLAT_VECTOR is
- // illegal and must be expanded. Since we know that the constants are
- // sign-extended 32-bit values, we use VMV_V_X_VL directly.
- bool IsRV32E64 =
- !Subtarget.is64Bit() && VecVT.getVectorElementType() == MVT::i64;
-
- if (!IsRV32E64) {
- SplatZero = DAG.getSplatVector(VecVT, DL, SplatZero);
- SplatTrueVal = DAG.getSplatVector(VecVT, DL, SplatTrueVal);
- } else {
- SplatZero =
- DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, DAG.getUNDEF(VecVT),
- SplatZero, DAG.getRegister(RISCV::X0, XLenVT));
- SplatTrueVal =
- DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, DAG.getUNDEF(VecVT),
- SplatTrueVal, DAG.getRegister(RISCV::X0, XLenVT));
- }
-
+ SDValue SplatZero = DAG.getConstant(0, DL, VecVT);
+ SDValue SplatTrueVal = DAG.getConstant(ExtTrueVal, DL, VecVT);
return DAG.getNode(ISD::VSELECT, DL, VecVT, Src, SplatTrueVal, SplatZero);
}
@@ -4303,6 +4282,10 @@
SDValue Mask, VL;
std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
+ MVT XLenVT = Subtarget.getXLenVT();
+ SDValue SplatZero = DAG.getConstant(0, DL, XLenVT);
+ SDValue SplatTrueVal = DAG.getConstant(ExtTrueVal, DL, XLenVT);
+
SplatZero = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT,
DAG.getUNDEF(ContainerVT), SplatZero, VL);
SplatTrueVal = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT,
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D121645.416214.patch
Type: text/x-patch
Size: 2165 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220317/b4b0577a/attachment.bin>
More information about the llvm-commits
mailing list