[PATCH] D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process

[ShihPo Hung via Phabricator via llvm-commits]

arcbbb updated this revision to Diff 416207.
arcbbb added a comment.

Updates:

1. Addresses @rogfer01's comment. Transforms TU+IMPLICIT_DEF to TA. This can be changed later if we have alternative idea.
2. Adds TU+IMPLICIT_DEF test cases by

      sed -i '/; CHECK.*/d' $file
      sed -i -e '/define.*@intrinsic_vf.\?cvt_mask/{
             h;
             s/define <vscale.*> @intrinsic_\(vf.\?cvt\)_mask\(.*\)(\(<vscale.*>\) %0, \(<vscale.*>\) %1, <vscale x \(.*\) x i1> %2, iXLen %3) \(.*\)/\
  define \3 @intrinsic_allone_\1_mask\2(\4 %1, iXLen %3) \6\
  entry:\
    %allone = call <vscale x \5 x i1> @llvm.riscv.vmset.nxv\5i1(\
      iXLen %3);/;
             x;
             n;n;N;N; N;N;N;N;N;
             H;
             x;
             s/%0/undef/g
             s/%1/%0/g
             s/%2/%allone/g
             s/%3/%1/g
             s/iXLen 1/iXLen 0/g
             x;
             G;}


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121881/new/

https://reviews.llvm.org/D121881

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/strict-vfcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/strict-vfcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/strict-vfcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/strict-vfcvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/strict-vfncvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/strict-vfncvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/strict-vfncvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/strict-vfncvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/strict-vfncvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/strict-vfwcvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/strict-vfwcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/strict-vfwcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/strict-vfwcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/strict-vfwcvt-xu-f.ll

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