[PATCH] D121768: [tablgen][X86] Auto-generate fields and trival interace for target features

[Kan Shengchen via Phabricator via llvm-commits]

skan added a comment.

In D121768#3388868 <https://reviews.llvm.org/D121768#3388868>, @skan wrote:

> In D121768#3388689 <https://reviews.llvm.org/D121768#3388689>, @tmatheson wrote:
>
>> This looks remarkably similar to an ARM/AArch64 patch I've had up for a couple of weeks: D120906 <https://reviews.llvm.org/D120906>
>>
>> The main differences seem to be:
>>
>> 1. I use a more general GET_SUBTARGETINFO_MACRO macro that can be expanded for other uses going forwards, rather than emitting the various bits of C++ directly.
>> 2. This patch makes a distinction between trivial/nontrivial members, why is this necessary?
>
> I'm sorry that I didn't notice your patch, otherwise I would comment on it rather than propose a patch.  Let me check the difference.

There are more differences

1. I copy the descriptions of the features to the generated header file but you just omit them
2. I also support the enum types, e.g

  bool hasAVX512() const { return X86SSELevel >= AVX512; }

3. This patch makes a distinction between trivial/nontrivial members & interface b/c some targets has some tricky interfaces, e.g

  `
  bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); }
  bool useAA() const override { return UseAA; }
  bool hasLAHFSAHF() const { return HasLAHFSAHF64 || !is64Bit(); }

It seems that you patch handle them incorrectly by now.

4. A field may be set to `true` by a feature while the default value of the field can either be `true` or `false` at the same time. So I provide a way to avoid generating field that is not zero-initialized.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D121768/new/

https://reviews.llvm.org/D121768