[PATCH] D121887: [RISCV] Teach VSETVLI insertion that it doesn't need to insert vsetvli for vlm.v and vsm.v in some cases.

[Jianjian Guan via Phabricator via llvm-commits]

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Unit-stride mask load and store instructions also have EEW=8. So add them to the switch case to avoid redundant VSETVLI.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121887

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp


Index: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -679,6 +679,20 @@
   switch (MI.getOpcode()) {
   default:
     return false;
+  case RISCV::PseudoVSM_V_B1:
+  case RISCV::PseudoVSM_V_B2:
+  case RISCV::PseudoVSM_V_B4:
+  case RISCV::PseudoVSM_V_B8:
+  case RISCV::PseudoVSM_V_B16:
+  case RISCV::PseudoVSM_V_B32:
+  case RISCV::PseudoVSM_V_B64:
+  case RISCV::PseudoVLM_V_B1:
+  case RISCV::PseudoVLM_V_B2:
+  case RISCV::PseudoVLM_V_B4:
+  case RISCV::PseudoVLM_V_B8:
+  case RISCV::PseudoVLM_V_B16:
+  case RISCV::PseudoVLM_V_B32:
+  case RISCV::PseudoVLM_V_B64:
   case RISCV::PseudoVLE8_V_M1:
   case RISCV::PseudoVLE8_V_M1_MASK:
   case RISCV::PseudoVLE8_V_M2:


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