[llvm] fb8d23b - [AMDGPU] Define new feature HasFlatScratchSVSMode. NFC.
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 16 12:59:45 PDT 2022
Author: Jay Foad
Date: 2022-03-16T19:54:02Z
New Revision: fb8d23b8e7d5c61f965fd87d820a60d6255e72d4
URL: https://github.com/llvm/llvm-project/commit/fb8d23b8e7d5c61f965fd87d820a60d6255e72d4
DIFF: https://github.com/llvm/llvm-project/commit/fb8d23b8e7d5c61f965fd87d820a60d6255e72d4.diff
LOG: [AMDGPU] Define new feature HasFlatScratchSVSMode. NFC.
This is by analogy with HasFlatScratchSTMode and is slightly more
informative than using isGFX940Plus.
Differential Revision: https://reviews.llvm.org/D121804
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPU.td
llvm/lib/Target/AMDGPU/FLATInstructions.td
llvm/lib/Target/AMDGPU/GCNSubtarget.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index dcaf02524bbc9..28acd6ef9156c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1396,6 +1396,8 @@ def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
AssemblerPredicate<(any_of FeatureGFX10_3Insts, FeatureGFX940Insts)>;
+def HasFlatScratchSVSMode : Predicate<"Subtarget->hasFlatScratchSVSMode()">,
+ AssemblerPredicate<(any_of FeatureGFX940Insts)>;
def HasGFX10_AEncoding : Predicate<"Subtarget->hasGFX10_AEncoding()">,
AssemblerPredicate<(all_of FeatureGFX10_AEncoding)>;
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td
index a2a9c3d7788b5..8c4404b77c8d6 100644
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -366,7 +366,7 @@ multiclass FLAT_Scratch_Load_Pseudo<string opName, RegisterClass regClass, bit H
def _SADDR : FLAT_Scratch_Load_Pseudo<opName, regClass, HasTiedOutput, 1>,
FlatScratchInst<opName, "SS">;
- let SubtargetPredicate = isGFX940Plus in
+ let SubtargetPredicate = HasFlatScratchSVSMode in
def _SVS : FLAT_Scratch_Load_Pseudo<opName, regClass, HasTiedOutput, 1, 1>,
FlatScratchInst<opName, "SVS">;
@@ -383,7 +383,7 @@ multiclass FLAT_Scratch_Store_Pseudo<string opName, RegisterClass regClass> {
def _SADDR : FLAT_Scratch_Store_Pseudo<opName, regClass, 1>,
FlatScratchInst<opName, "SS">;
- let SubtargetPredicate = isGFX940Plus in
+ let SubtargetPredicate = HasFlatScratchSVSMode in
def _SVS : FLAT_Scratch_Store_Pseudo<opName, regClass, 1, 1>,
FlatScratchInst<opName, "SVS">;
@@ -1272,7 +1272,7 @@ multiclass ScratchFLATLoadPats<FLAT_Pseudo inst, SDPatternOperator node, ValueTy
}
def : ScratchLoadSVaddrPat<!cast<FLAT_Pseudo>(!cast<string>(inst)#"_SVS"), node, vt> {
- let SubtargetPredicate = isGFX940Plus;
+ let SubtargetPredicate = HasFlatScratchSVSMode;
let AddedComplexity = 27;
}
}
@@ -1288,7 +1288,7 @@ multiclass ScratchFLATStorePats<FLAT_Pseudo inst, SDPatternOperator node,
}
def : ScratchStoreSVaddrPat<!cast<FLAT_Pseudo>(!cast<string>(inst)#"_SVS"), node, vt> {
- let SubtargetPredicate = isGFX940Plus;
+ let SubtargetPredicate = HasFlatScratchSVSMode;
let AddedComplexity = 27;
}
}
@@ -1303,7 +1303,7 @@ multiclass ScratchFLATLoadPats_D16<FLAT_Pseudo inst, SDPatternOperator node, Val
}
def : ScratchLoadSVaddrPat_D16 <!cast<FLAT_Pseudo>(!cast<string>(inst)#"_SVS"), node, vt> {
- let SubtargetPredicate = isGFX940Plus;
+ let SubtargetPredicate = HasFlatScratchSVSMode;
let AddedComplexity = 27;
}
}
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 2b48ba6024b15..d48327a4aaac3 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -571,6 +571,8 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
return hasFlatScratchInsts() && (hasGFX10_3Insts() || hasGFX940Insts());
}
+ bool hasFlatScratchSVSMode() const { return GFX940Insts; }
+
bool hasScalarFlatScratchInsts() const {
return ScalarFlatScratchInsts;
}
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