[PATCH] D121840: [RFC][WIP][RISCV] Fold ADDI of LLA + Load/Store code sequences

[Luís Marques via Phabricator via llvm-commits]

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RFC: I'm not sure this is the best approach for achieving this...?

For medany code models we aren't folding the ADDI offset of the AUIPC+ADDI+Load/Store (i.e. LLA+Load/Store) into the Load/Store offset. We have a pass for that but it runs before register allocation, while the LLA pseudoinstruction expansion runs just before code emission. As an alternative to this patch, I'm not sure either of those could be changed to be able to run in the opposite order and handle this case?

(This is currently a WIP. TODO: implement stores, etc.)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121840

Files:
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/codemodel-lowering.ll

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