[llvm] 83413bb - [x86] reduce indentation; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2022-03-16T13:39:02-04:00
New Revision: 83413bb617aa5a54f6f8f71029c251c709602e1f

URL: https://github.com/llvm/llvm-project/commit/83413bb617aa5a54f6f8f71029c251c709602e1f
DIFF: https://github.com/llvm/llvm-project/commit/83413bb617aa5a54f6f8f71029c251c709602e1f.diff

LOG: [x86] reduce indentation; NFC

We may be able to refine the conditions for these transforms ( D120648 ).

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 0380124434a85..a02fdf33dff6b 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -5617,55 +5617,53 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
       // Check if we can replace AND+IMM64 with a shift. This is possible for
       // masks like 0xFF000000 or 0x00FFFFFF and if we care only about the zero
       // flag.
-      if (CmpVT == MVT::i64 && !isInt<32>(Mask) &&
+      if (CmpVT == MVT::i64 && !isInt<32>(Mask) && isShiftedMask_64(Mask) &&
           onlyUsesZeroFlag(SDValue(Node, 0))) {
         unsigned ShiftOpcode = ISD::DELETED_NODE;
         unsigned ShiftAmt;
         unsigned SubRegIdx;
         MVT SubRegVT;
         unsigned TestOpcode;
-        if (isShiftedMask_64(Mask)) {
-          unsigned LeadingZeros = countLeadingZeros(Mask);
-          unsigned TrailingZeros = countTrailingZeros(Mask);
+        unsigned LeadingZeros = countLeadingZeros(Mask);
+        unsigned TrailingZeros = countTrailingZeros(Mask);
+        if (LeadingZeros == 0) {
           // If the mask covers the most significant bit, then we can replace
           // TEST+AND with a SHR and check eflags.
           // This emits a redundant TEST which is subsequently eliminated.
-          if (LeadingZeros == 0) {
+          ShiftOpcode = X86::SHR64ri;
+          ShiftAmt = TrailingZeros;
+          SubRegIdx = 0;
+          TestOpcode = X86::TEST64rr;
+        } else if (TrailingZeros == 0) {
+          // If the mask covers the least significant bit, then we can replace
+          // TEST+AND with a SHL and check eflags.
+          // This emits a redundant TEST which is subsequently eliminated.
+          ShiftOpcode = X86::SHL64ri;
+          ShiftAmt = LeadingZeros;
+          SubRegIdx = 0;
+          TestOpcode = X86::TEST64rr;
+        } else if (MaskC->hasOneUse()) {
+          // If the mask is 8/16 or 32bits wide, then we can replace it with
+          // a SHR and a TEST8rr/TEST16rr/TEST32rr.
+          unsigned PopCount = 64 - LeadingZeros - TrailingZeros;
+          if (PopCount == 8) {
+            ShiftOpcode = X86::SHR64ri;
+            ShiftAmt = TrailingZeros;
+            SubRegIdx = X86::sub_8bit;
+            SubRegVT = MVT::i8;
+            TestOpcode = X86::TEST8rr;
+          } else if (PopCount == 16) {
+            ShiftOpcode = X86::SHR64ri;
+            ShiftAmt = TrailingZeros;
+            SubRegIdx = X86::sub_16bit;
+            SubRegVT = MVT::i16;
+            TestOpcode = X86::TEST16rr;
+          } else if (PopCount == 32) {
             ShiftOpcode = X86::SHR64ri;
             ShiftAmt = TrailingZeros;
-            SubRegIdx = 0;
-            TestOpcode = X86::TEST64rr;
-            // If the mask covers the least signifcant bit, then we can replace
-            // TEST+AND with a SHL and check eflags.
-            // This emits a redundant TEST which is subsequently eliminated.
-          } else if (TrailingZeros == 0) {
-            ShiftOpcode = X86::SHL64ri;
-            ShiftAmt = LeadingZeros;
-            SubRegIdx = 0;
-            TestOpcode = X86::TEST64rr;
-          } else if (MaskC->hasOneUse()) {
-            // If the mask is 8/16 or 32bits wide, then we can replace it with
-            // a SHR and a TEST8rr/TEST16rr/TEST32rr.
-            unsigned PopCount = 64 - LeadingZeros - TrailingZeros;
-            if (PopCount == 8) {
-              ShiftOpcode = X86::SHR64ri;
-              ShiftAmt = TrailingZeros;
-              SubRegIdx = X86::sub_8bit;
-              SubRegVT = MVT::i8;
-              TestOpcode = X86::TEST8rr;
-            } else if (PopCount == 16) {
-              ShiftOpcode = X86::SHR64ri;
-              ShiftAmt = TrailingZeros;
-              SubRegIdx = X86::sub_16bit;
-              SubRegVT = MVT::i16;
-              TestOpcode = X86::TEST16rr;
-            } else if (PopCount == 32) {
-              ShiftOpcode = X86::SHR64ri;
-              ShiftAmt = TrailingZeros;
-              SubRegIdx = X86::sub_32bit;
-              SubRegVT = MVT::i32;
-              TestOpcode = X86::TEST32rr;
-            }
+            SubRegIdx = X86::sub_32bit;
+            SubRegVT = MVT::i32;
+            TestOpcode = X86::TEST32rr;
           }
         }
         if (ShiftOpcode != ISD::DELETED_NODE) {