[llvm] c7dc9db - [VE] Remove output to /dev/stdout
Jake Egan via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 16 08:42:21 PDT 2022
Author: Jake Egan
Date: 2022-03-16T11:42:09-04:00
New Revision: c7dc9dbaff3a4cda7c23088e77a078a3b57af545
URL: https://github.com/llvm/llvm-project/commit/c7dc9dbaff3a4cda7c23088e77a078a3b57af545
DIFF: https://github.com/llvm/llvm-project/commit/c7dc9dbaff3a4cda7c23088e77a078a3b57af545.diff
LOG: [VE] Remove output to /dev/stdout
Sending output to /dev/stdout on AIX gets an llc permission denied error, so this patch removes this from the tests.
Reviewed By: simoll, hubert.reinterpretcast
Differential Revision: https://reviews.llvm.org/D121799
Added:
Modified:
llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll
llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll
llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll
llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll
llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll
llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll
llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll
llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll
llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll
llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll b/llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll
index a0ad0cfbbb498..3648850697fbc 100644
--- a/llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vector.reduce.add.v256i64(<256 x i64>)
diff --git a/llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll b/llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll
index 7186ce42c04cb..53af0f9c40342 100644
--- a/llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vector.reduce.and.v256i64(<256 x i64>)
diff --git a/llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll b/llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll
index 8f8308d047f9f..f30b77449b04d 100644
--- a/llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vector.reduce.or.v256i64(<256 x i64>)
diff --git a/llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll b/llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll
index abb86645b74aa..822b541e0b047 100644
--- a/llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vector.reduce.smax.v256i64(<256 x i64>)
diff --git a/llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll b/llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll
index ad8c7ad735020..47b291f3ecab6 100644
--- a/llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vector.reduce.xor.v256i64(<256 x i64>)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll
index 97ea68df3e09d..9e54053e9dd63 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vp.reduce.add.v256i64(i64, <256 x i64>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll
index c1dc3841e7f2f..af2868a0c438a 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vp.reduce.and.v256i64(i64, <256 x i64>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll
index 41677f4c682a6..85f02a37a354f 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vp.reduce.or.v256i64(i64, <256 x i64>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll
index 9791a9aa27b0e..766dd723dc9f1 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vp.reduce.smax.v256i64(i64, <256 x i64>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll
index 233abb92c7f53..ac2de57b6baca 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
+; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vp.reduce.xor.v256i64(i64, <256 x i64>, <256 x i1>, i32)
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