[llvm] fb81f06 - [AMDGPU] Calculate RegWidth in bits in AsmParser
Joe Nash via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 16 08:19:22 PDT 2022
Author: Joe Nash
Date: 2022-03-16T10:52:14-04:00
New Revision: fb81f06f63af9f57be66f1ef05fd47397f999f39
URL: https://github.com/llvm/llvm-project/commit/fb81f06f63af9f57be66f1ef05fd47397f999f39
DIFF: https://github.com/llvm/llvm-project/commit/fb81f06f63af9f57be66f1ef05fd47397f999f39.diff
LOG: [AMDGPU] Calculate RegWidth in bits in AsmParser
NFC. Switch from calculations based on dwords to bits, to be more
flexible.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D121730
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 4e5abba7b58f6..f48c3dae47812 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -35,6 +35,7 @@
#include "llvm/Support/AMDHSAKernelDescriptor.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/MachineValueType.h"
+#include "llvm/Support/MathExtras.h"
#include "llvm/Support/TargetParser.h"
using namespace llvm;
@@ -1189,12 +1190,20 @@ class KernelScopeInfo {
}
}
- void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex, unsigned RegWidth) {
+ void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex,
+ unsigned RegWidth) {
switch (RegKind) {
- case IS_SGPR: usesSgprAt(DwordRegIndex + RegWidth - 1); break;
- case IS_AGPR: usesAgprAt(DwordRegIndex + RegWidth - 1); break;
- case IS_VGPR: usesVgprAt(DwordRegIndex + RegWidth - 1); break;
- default: break;
+ case IS_SGPR:
+ usesSgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);
+ break;
+ case IS_AGPR:
+ usesAgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);
+ break;
+ case IS_VGPR:
+ usesVgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);
+ break;
+ default:
+ break;
}
}
};
@@ -2249,52 +2258,86 @@ static int getRegClass(RegisterKind Is, unsigned RegWidth) {
if (Is == IS_VGPR) {
switch (RegWidth) {
default: return -1;
- case 1: return AMDGPU::VGPR_32RegClassID;
- case 2: return AMDGPU::VReg_64RegClassID;
- case 3: return AMDGPU::VReg_96RegClassID;
- case 4: return AMDGPU::VReg_128RegClassID;
- case 5: return AMDGPU::VReg_160RegClassID;
- case 6: return AMDGPU::VReg_192RegClassID;
- case 7: return AMDGPU::VReg_224RegClassID;
- case 8: return AMDGPU::VReg_256RegClassID;
- case 16: return AMDGPU::VReg_512RegClassID;
- case 32: return AMDGPU::VReg_1024RegClassID;
+ case 32:
+ return AMDGPU::VGPR_32RegClassID;
+ case 64:
+ return AMDGPU::VReg_64RegClassID;
+ case 96:
+ return AMDGPU::VReg_96RegClassID;
+ case 128:
+ return AMDGPU::VReg_128RegClassID;
+ case 160:
+ return AMDGPU::VReg_160RegClassID;
+ case 192:
+ return AMDGPU::VReg_192RegClassID;
+ case 224:
+ return AMDGPU::VReg_224RegClassID;
+ case 256:
+ return AMDGPU::VReg_256RegClassID;
+ case 512:
+ return AMDGPU::VReg_512RegClassID;
+ case 1024:
+ return AMDGPU::VReg_1024RegClassID;
}
} else if (Is == IS_TTMP) {
switch (RegWidth) {
default: return -1;
- case 1: return AMDGPU::TTMP_32RegClassID;
- case 2: return AMDGPU::TTMP_64RegClassID;
- case 4: return AMDGPU::TTMP_128RegClassID;
- case 8: return AMDGPU::TTMP_256RegClassID;
- case 16: return AMDGPU::TTMP_512RegClassID;
+ case 32:
+ return AMDGPU::TTMP_32RegClassID;
+ case 64:
+ return AMDGPU::TTMP_64RegClassID;
+ case 128:
+ return AMDGPU::TTMP_128RegClassID;
+ case 256:
+ return AMDGPU::TTMP_256RegClassID;
+ case 512:
+ return AMDGPU::TTMP_512RegClassID;
}
} else if (Is == IS_SGPR) {
switch (RegWidth) {
default: return -1;
- case 1: return AMDGPU::SGPR_32RegClassID;
- case 2: return AMDGPU::SGPR_64RegClassID;
- case 3: return AMDGPU::SGPR_96RegClassID;
- case 4: return AMDGPU::SGPR_128RegClassID;
- case 5: return AMDGPU::SGPR_160RegClassID;
- case 6: return AMDGPU::SGPR_192RegClassID;
- case 7: return AMDGPU::SGPR_224RegClassID;
- case 8: return AMDGPU::SGPR_256RegClassID;
- case 16: return AMDGPU::SGPR_512RegClassID;
+ case 32:
+ return AMDGPU::SGPR_32RegClassID;
+ case 64:
+ return AMDGPU::SGPR_64RegClassID;
+ case 96:
+ return AMDGPU::SGPR_96RegClassID;
+ case 128:
+ return AMDGPU::SGPR_128RegClassID;
+ case 160:
+ return AMDGPU::SGPR_160RegClassID;
+ case 192:
+ return AMDGPU::SGPR_192RegClassID;
+ case 224:
+ return AMDGPU::SGPR_224RegClassID;
+ case 256:
+ return AMDGPU::SGPR_256RegClassID;
+ case 512:
+ return AMDGPU::SGPR_512RegClassID;
}
} else if (Is == IS_AGPR) {
switch (RegWidth) {
default: return -1;
- case 1: return AMDGPU::AGPR_32RegClassID;
- case 2: return AMDGPU::AReg_64RegClassID;
- case 3: return AMDGPU::AReg_96RegClassID;
- case 4: return AMDGPU::AReg_128RegClassID;
- case 5: return AMDGPU::AReg_160RegClassID;
- case 6: return AMDGPU::AReg_192RegClassID;
- case 7: return AMDGPU::AReg_224RegClassID;
- case 8: return AMDGPU::AReg_256RegClassID;
- case 16: return AMDGPU::AReg_512RegClassID;
- case 32: return AMDGPU::AReg_1024RegClassID;
+ case 32:
+ return AMDGPU::AGPR_32RegClassID;
+ case 64:
+ return AMDGPU::AReg_64RegClassID;
+ case 96:
+ return AMDGPU::AReg_96RegClassID;
+ case 128:
+ return AMDGPU::AReg_128RegClassID;
+ case 160:
+ return AMDGPU::AReg_160RegClassID;
+ case 192:
+ return AMDGPU::AReg_192RegClassID;
+ case 224:
+ return AMDGPU::AReg_224RegClassID;
+ case 256:
+ return AMDGPU::AReg_256RegClassID;
+ case 512:
+ return AMDGPU::AReg_512RegClassID;
+ case 1024:
+ return AMDGPU::AReg_1024RegClassID;
}
}
return -1;
@@ -2381,32 +2424,32 @@ bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth,
case IS_SPECIAL:
if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) {
Reg = AMDGPU::EXEC;
- RegWidth = 2;
+ RegWidth = 64;
return true;
}
if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) {
Reg = AMDGPU::FLAT_SCR;
- RegWidth = 2;
+ RegWidth = 64;
return true;
}
if (Reg == AMDGPU::XNACK_MASK_LO && Reg1 == AMDGPU::XNACK_MASK_HI) {
Reg = AMDGPU::XNACK_MASK;
- RegWidth = 2;
+ RegWidth = 64;
return true;
}
if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) {
Reg = AMDGPU::VCC;
- RegWidth = 2;
+ RegWidth = 64;
return true;
}
if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) {
Reg = AMDGPU::TBA;
- RegWidth = 2;
+ RegWidth = 64;
return true;
}
if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) {
Reg = AMDGPU::TMA;
- RegWidth = 2;
+ RegWidth = 64;
return true;
}
Error(Loc, "register does not fit in the list");
@@ -2415,11 +2458,11 @@ bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth,
case IS_SGPR:
case IS_AGPR:
case IS_TTMP:
- if (Reg1 != Reg + RegWidth) {
+ if (Reg1 != Reg + RegWidth / 32) {
Error(Loc, "registers in a list must have consecutive indices");
return false;
}
- RegWidth++;
+ RegWidth += 32;
return true;
default:
llvm_unreachable("unexpected register kind");
@@ -2508,7 +2551,7 @@ AMDGPUAsmParser::getRegularReg(RegisterKind RegKind,
if (RegKind == IS_SGPR || RegKind == IS_TTMP) {
// SGPR and TTMP registers must be aligned.
// Max required alignment is 4 dwords.
- AlignSize = std::min(RegWidth, 4u);
+ AlignSize = std::min(RegWidth / 32, 4u);
}
if (RegNum % AlignSize != 0) {
@@ -2533,8 +2576,7 @@ AMDGPUAsmParser::getRegularReg(RegisterKind RegKind,
return RC.getRegister(RegIdx);
}
-bool
-AMDGPUAsmParser::ParseRegRange(unsigned& Num, unsigned& Width) {
+bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth) {
int64_t RegLo, RegHi;
if (!skipToken(AsmToken::LBrac, "missing register index"))
return false;
@@ -2572,7 +2614,7 @@ AMDGPUAsmParser::ParseRegRange(unsigned& Num, unsigned& Width) {
}
Num = static_cast<unsigned>(RegLo);
- Width = (RegHi - RegLo) + 1;
+ RegWidth = 32 * ((RegHi - RegLo) + 1);
return true;
}
@@ -2583,7 +2625,7 @@ unsigned AMDGPUAsmParser::ParseSpecialReg(RegisterKind &RegKind,
unsigned Reg = getSpecialRegForName(getTokenStr());
if (Reg) {
RegNum = 0;
- RegWidth = 1;
+ RegWidth = 32;
RegKind = IS_SPECIAL;
Tokens.push_back(getToken());
lex(); // skip register name
@@ -2615,7 +2657,7 @@ unsigned AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind,
Error(Loc, "invalid register index");
return AMDGPU::NoRegister;
}
- RegWidth = 1;
+ RegWidth = 32;
} else {
// Range of registers: v[XX:YY]. ":YY" is optional.
if (!ParseRegRange(RegNum, RegWidth))
@@ -2641,7 +2683,7 @@ unsigned AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
auto Loc = getLoc();
if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth))
return AMDGPU::NoRegister;
- if (RegWidth != 1) {
+ if (RegWidth != 32) {
Error(Loc, "expected a single 32-bit register");
return AMDGPU::NoRegister;
}
@@ -2656,7 +2698,7 @@ unsigned AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
Tokens)) {
return AMDGPU::NoRegister;
}
- if (NextRegWidth != 1) {
+ if (NextRegWidth != 32) {
Error(Loc, "expected a single 32-bit register");
return AMDGPU::NoRegister;
}
@@ -2759,7 +2801,7 @@ bool AMDGPUAsmParser::updateGprCountSymbols(RegisterKind RegKind,
return true;
MCSymbol *Sym = getContext().getOrCreateSymbol(*SymbolName);
- int64_t NewMax = DwordRegIndex + RegWidth - 1;
+ int64_t NewMax = DwordRegIndex + divideCeil(RegWidth, 32) - 1;
int64_t OldCount;
if (!Sym->isVariable())
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