[llvm] 37b3783 - [NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 16 05:26:07 PDT 2022
Author: Shengchen Kan
Date: 2022-03-16T20:25:42+08:00
New Revision: 37b378386eefab39ef570db6172a8b8e660d7bfb
URL: https://github.com/llvm/llvm-project/commit/37b378386eefab39ef570db6172a8b8e660d7bfb
DIFF: https://github.com/llvm/llvm-project/commit/37b378386eefab39ef570db6172a8b8e660d7bfb.diff
LOG: [NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments
Added:
Modified:
llvm/include/llvm/CodeGen/MachineInstr.h
llvm/lib/CodeGen/EarlyIfConversion.cpp
llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/lib/CodeGen/InlineSpiller.cpp
llvm/lib/CodeGen/LiveRangeEdit.cpp
llvm/lib/CodeGen/MachineBasicBlock.cpp
llvm/lib/CodeGen/MachineInstr.cpp
llvm/lib/CodeGen/MachineLoopUtils.cpp
llvm/lib/CodeGen/MachineVerifier.cpp
llvm/lib/CodeGen/ModuloSchedule.cpp
llvm/lib/CodeGen/PeepholeOptimizer.cpp
llvm/lib/CodeGen/ProcessImplicitDefs.cpp
llvm/lib/CodeGen/RegisterCoalescer.cpp
llvm/lib/CodeGen/TailDuplicator.cpp
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/lib/CodeGen/UnreachableBlockElim.cpp
llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
llvm/lib/Target/ARC/ARCOptAddrMode.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMInstructionSelector.cpp
llvm/lib/Target/ARM/ARMSLSHardening.cpp
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
llvm/lib/Target/AVR/AVRRegisterInfo.cpp
llvm/lib/Target/CSKY/CSKYRegisterInfo.cpp
llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/lib/Target/Hexagon/HexagonPeephole.cpp
llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp
llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
llvm/lib/Target/Mips/MipsBranchExpansion.cpp
llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
llvm/lib/Target/Mips/MipsInstrInfo.cpp
llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
llvm/lib/Target/WebAssembly/WebAssemblyFixBrTableDefaults.cpp
llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
llvm/lib/Target/X86/X86ExpandPseudo.cpp
llvm/lib/Target/X86/X86FloatingPoint.cpp
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstructionSelector.cpp
llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index 26d3d76dfe59e..e36f68b1c908b 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -1746,7 +1746,7 @@ class MachineInstr
/// Erase an operand from an instruction, leaving it with one
/// fewer operand than it started with.
- void RemoveOperand(unsigned OpNo);
+ void removeOperand(unsigned OpNo);
/// Clear this MachineInstr's memory reference descriptor list. This resets
/// the memrefs to their most conservative state. This should be used only
@@ -1865,12 +1865,12 @@ class MachineInstr
/// Unlink all of the register operands in this instruction from their
/// respective use lists. This requires that the operands already be on their
/// use lists.
- void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
+ void removeRegOperandsFromUseLists(MachineRegisterInfo&);
/// Add all of the register operands in this instruction from their
/// respective use lists. This requires that the operands not be on their
/// use lists yet.
- void AddRegOperandsToUseLists(MachineRegisterInfo&);
+ void addRegOperandsToUseLists(MachineRegisterInfo&);
/// Slow path for hasProperty when we're dealing with a bundle.
bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp
index c891d35746049..32858d0433837 100644
--- a/llvm/lib/CodeGen/EarlyIfConversion.cpp
+++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp
@@ -663,8 +663,8 @@ void SSAIfConv::rewritePHIOperands() {
PI.PHI->getOperand(i-1).setMBB(Head);
PI.PHI->getOperand(i-2).setReg(DstReg);
} else if (MBB == getFPred()) {
- PI.PHI->RemoveOperand(i-1);
- PI.PHI->RemoveOperand(i-2);
+ PI.PHI->removeOperand(i-1);
+ PI.PHI->removeOperand(i-2);
}
}
LLVM_DEBUG(dbgs() << " --> " << *PI.PHI);
diff --git a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
index 02ad3f5da35d3..086b4a4dcc47b 100644
--- a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
+++ b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
@@ -102,8 +102,8 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
if (MI->allDefsAreDead()) {
MI->setDesc(TII->get(TargetOpcode::KILL));
- MI->RemoveOperand(3); // SubIdx
- MI->RemoveOperand(1); // Imm
+ MI->removeOperand(3); // SubIdx
+ MI->removeOperand(1); // Imm
LLVM_DEBUG(dbgs() << "subreg: replaced by: " << *MI);
return true;
}
@@ -115,8 +115,8 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
// We must leave %rax live.
if (DstReg != InsReg) {
MI->setDesc(TII->get(TargetOpcode::KILL));
- MI->RemoveOperand(3); // SubIdx
- MI->RemoveOperand(1); // Imm
+ MI->removeOperand(3); // SubIdx
+ MI->removeOperand(1); // Imm
LLVM_DEBUG(dbgs() << "subreg: replace by: " << *MI);
return true;
}
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 8f74d386e3f59..674557b1caedf 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -4083,7 +4083,7 @@ void CombinerHelper::applyFunnelShiftToRotate(MachineInstr &MI) {
Observer.changingInstr(MI);
MI.setDesc(Builder.getTII().get(IsFSHL ? TargetOpcode::G_ROTL
: TargetOpcode::G_ROTR));
- MI.RemoveOperand(2);
+ MI.removeOperand(2);
Observer.changedInstr(MI);
}
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 1ad421f584c51..8dd8f9952ad30 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -3317,7 +3317,7 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
Observer.changingInstr(MI);
const auto &TII = MIRBuilder.getTII();
MI.setDesc(TII.get(TargetOpcode::G_MUL));
- MI.RemoveOperand(1);
+ MI.removeOperand(1);
Observer.changedInstr(MI);
auto HiPart = MIRBuilder.buildInstr(Opcode, {Ty}, {LHS, RHS});
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index d12dc0a6b1d7c..43b30fdd8909f 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -963,7 +963,7 @@ foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>> Ops,
if (!MO.isReg() || !MO.isImplicit())
break;
if (MO.getReg() == ImpReg)
- FoldMI->RemoveOperand(i - 1);
+ FoldMI->removeOperand(i - 1);
}
LLVM_DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MIS.end(), LIS,
@@ -1607,7 +1607,7 @@ void HoistSpillHelper::hoistAllSpills() {
for (unsigned i = RMEnt->getNumOperands(); i; --i) {
MachineOperand &MO = RMEnt->getOperand(i - 1);
if (MO.isReg() && MO.isImplicit() && MO.isDef() && !MO.isDead())
- RMEnt->RemoveOperand(i - 1);
+ RMEnt->removeOperand(i - 1);
}
}
Edit.eliminateDeadDefs(SpillsToRm, None, AA);
diff --git a/llvm/lib/CodeGen/LiveRangeEdit.cpp b/llvm/lib/CodeGen/LiveRangeEdit.cpp
index 05768140cbdf2..58eb4110f153f 100644
--- a/llvm/lib/CodeGen/LiveRangeEdit.cpp
+++ b/llvm/lib/CodeGen/LiveRangeEdit.cpp
@@ -371,7 +371,7 @@ void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink,
const MachineOperand &MO = MI->getOperand(i-1);
if (MO.isReg() && Register::isPhysicalRegister(MO.getReg()))
continue;
- MI->RemoveOperand(i-1);
+ MI->removeOperand(i-1);
}
LLVM_DEBUG(dbgs() << "Converted physregs to:\t" << *MI);
} else {
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 992ba27785011..9f6be9aba632c 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -132,7 +132,7 @@ void ilist_callback_traits<MachineBasicBlock>::addNodeToList(
// Make sure the instructions have their operands in the reginfo lists.
MachineRegisterInfo &RegInfo = MF.getRegInfo();
for (MachineInstr &MI : N->instrs())
- MI.AddRegOperandsToUseLists(RegInfo);
+ MI.addRegOperandsToUseLists(RegInfo);
}
void ilist_callback_traits<MachineBasicBlock>::removeNodeFromList(
@@ -150,7 +150,7 @@ void ilist_traits<MachineInstr>::addNodeToList(MachineInstr *N) {
// Add the instruction's register operands to their corresponding
// use/def lists.
MachineFunction *MF = Parent->getParent();
- N->AddRegOperandsToUseLists(MF->getRegInfo());
+ N->addRegOperandsToUseLists(MF->getRegInfo());
MF->handleInsertion(*N);
}
@@ -162,7 +162,7 @@ void ilist_traits<MachineInstr>::removeNodeFromList(MachineInstr *N) {
// Remove from the use/def lists.
if (MachineFunction *MF = N->getMF()) {
MF->handleRemoval(*N);
- N->RemoveRegOperandsFromUseLists(MF->getRegInfo());
+ N->removeRegOperandsFromUseLists(MF->getRegInfo());
}
N->setParent(nullptr);
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 54814035ab736..90156742f43bc 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -146,19 +146,13 @@ MachineRegisterInfo *MachineInstr::getRegInfo() {
return nullptr;
}
-/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
-/// this instruction from their respective use lists. This requires that the
-/// operands already be on their use lists.
-void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
+void MachineInstr::removeRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
for (MachineOperand &MO : operands())
if (MO.isReg())
MRI.removeRegOperandFromUseList(&MO);
}
-/// AddRegOperandsToUseLists - Add all of the register operands in
-/// this instruction from their respective use lists. This requires that the
-/// operands not be on their use lists yet.
-void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
+void MachineInstr::addRegOperandsToUseLists(MachineRegisterInfo &MRI) {
for (MachineOperand &MO : operands())
if (MO.isReg())
MRI.addRegOperandToUseList(&MO);
@@ -279,10 +273,7 @@ void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
}
}
-/// RemoveOperand - Erase an operand from an instruction, leaving it with one
-/// fewer operand than it started with.
-///
-void MachineInstr::RemoveOperand(unsigned OpNo) {
+void MachineInstr::removeOperand(unsigned OpNo) {
assert(OpNo < getNumOperands() && "Invalid operand number");
untieRegOperand(OpNo);
@@ -1883,7 +1874,7 @@ bool MachineInstr::addRegisterKilled(Register IncomingReg,
unsigned OpIdx = DeadOps.back();
if (getOperand(OpIdx).isImplicit() &&
(!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
- RemoveOperand(OpIdx);
+ removeOperand(OpIdx);
else
getOperand(OpIdx).setIsKill(false);
DeadOps.pop_back();
@@ -1948,7 +1939,7 @@ bool MachineInstr::addRegisterDead(Register Reg,
unsigned OpIdx = DeadOps.back();
if (getOperand(OpIdx).isImplicit() &&
(!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
- RemoveOperand(OpIdx);
+ removeOperand(OpIdx);
else
getOperand(OpIdx).setIsDead(false);
DeadOps.pop_back();
diff --git a/llvm/lib/CodeGen/MachineLoopUtils.cpp b/llvm/lib/CodeGen/MachineLoopUtils.cpp
index 882382e5a9714..94f25357a25c0 100644
--- a/llvm/lib/CodeGen/MachineLoopUtils.cpp
+++ b/llvm/lib/CodeGen/MachineLoopUtils.cpp
@@ -89,15 +89,15 @@ MachineBasicBlock *llvm::PeelSingleBlockLoop(LoopPeelDirection Direction,
if (Remaps.count(R))
R = Remaps[R];
OrigPhi.getOperand(InitRegIdx).setReg(R);
- MI.RemoveOperand(LoopRegIdx + 1);
- MI.RemoveOperand(LoopRegIdx + 0);
+ MI.removeOperand(LoopRegIdx + 1);
+ MI.removeOperand(LoopRegIdx + 0);
} else {
// When peeling back, the initial value is the loop-carried value from
// the original loop.
Register LoopReg = OrigPhi.getOperand(LoopRegIdx).getReg();
MI.getOperand(LoopRegIdx).setReg(LoopReg);
- MI.RemoveOperand(InitRegIdx + 1);
- MI.RemoveOperand(InitRegIdx + 0);
+ MI.removeOperand(InitRegIdx + 1);
+ MI.removeOperand(InitRegIdx + 0);
}
}
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 02181d8231982..2086157f6434f 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -443,7 +443,7 @@ unsigned MachineVerifier::verify(const MachineFunction &MF) {
for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
const MachineOperand &Op = MI.getOperand(I);
if (Op.getParent() != &MI) {
- // Make sure to use correct addOperand / RemoveOperand / ChangeTo
+ // Make sure to use correct addOperand / removeOperand / ChangeTo
// functions when replacing operands of a MachineInstr.
report("Instruction has operand with wrong parent set", &MI);
}
diff --git a/llvm/lib/CodeGen/ModuloSchedule.cpp b/llvm/lib/CodeGen/ModuloSchedule.cpp
index 0224e0797c1ad..b974fa9846f25 100644
--- a/llvm/lib/CodeGen/ModuloSchedule.cpp
+++ b/llvm/lib/CodeGen/ModuloSchedule.cpp
@@ -814,8 +814,8 @@ static void removePhis(MachineBasicBlock *BB, MachineBasicBlock *Incoming) {
break;
for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2)
if (MI.getOperand(i + 1).getMBB() == Incoming) {
- MI.RemoveOperand(i + 1);
- MI.RemoveOperand(i);
+ MI.removeOperand(i + 1);
+ MI.removeOperand(i);
break;
}
}
@@ -1930,8 +1930,8 @@ void PeelingModuloScheduleExpander::fixupBranches() {
// blocks. Leave it to unreachable-block-elim to clean up.
Prolog->removeSuccessor(Fallthrough);
for (MachineInstr &P : Fallthrough->phis()) {
- P.RemoveOperand(2);
- P.RemoveOperand(1);
+ P.removeOperand(2);
+ P.removeOperand(1);
}
TII->insertUnconditionalBranch(*Prolog, Epilog, DebugLoc());
KernelDisposed = true;
@@ -1940,8 +1940,8 @@ void PeelingModuloScheduleExpander::fixupBranches() {
// Prolog always falls through; remove incoming values in epilog.
Prolog->removeSuccessor(Epilog);
for (MachineInstr &P : Epilog->phis()) {
- P.RemoveOperand(4);
- P.RemoveOperand(3);
+ P.removeOperand(4);
+ P.removeOperand(3);
}
}
}
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index 449726beb9399..1b047489bf4ca 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -1021,7 +1021,7 @@ class ExtractSubregRewriter : public Rewriter {
CurrentSrcIdx = -1;
// Rewrite the operation as a COPY.
// Get rid of the sub-register index.
- CopyLike.RemoveOperand(2);
+ CopyLike.removeOperand(2);
// Morph the operation into a COPY.
CopyLike.setDesc(TII.get(TargetOpcode::COPY));
return true;
diff --git a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
index 440e40992dd6f..117ee59ac239a 100644
--- a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
+++ b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
@@ -125,7 +125,7 @@ void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
// Using instr wasn't found, it could be in another block.
// Leave the physreg IMPLICIT_DEF, but trim any extra operands.
for (unsigned i = MI->getNumOperands() - 1; i; --i)
- MI->RemoveOperand(i);
+ MI->removeOperand(i);
LLVM_DEBUG(dbgs() << "Keeping physreg: " << *MI);
}
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index a917b0d27d4af..930d053244408 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -1647,7 +1647,7 @@ MachineInstr *RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
for (unsigned i = CopyMI->getNumOperands(); i != 0; --i) {
MachineOperand &MO = CopyMI->getOperand(i-1);
if (MO.isReg() && MO.isUse())
- CopyMI->RemoveOperand(i-1);
+ CopyMI->removeOperand(i-1);
}
LLVM_DEBUG(dbgs() << "\tReplaced copy of <undef> value with an "
"implicit def\n");
diff --git a/llvm/lib/CodeGen/TailDuplicator.cpp b/llvm/lib/CodeGen/TailDuplicator.cpp
index c8657a97c1bf6..d034d0a22e04d 100644
--- a/llvm/lib/CodeGen/TailDuplicator.cpp
+++ b/llvm/lib/CodeGen/TailDuplicator.cpp
@@ -368,8 +368,8 @@ void TailDuplicator::processPHI(
return;
// Remove PredBB from the PHI node.
- MI->RemoveOperand(SrcOpIdx + 1);
- MI->RemoveOperand(SrcOpIdx);
+ MI->removeOperand(SrcOpIdx + 1);
+ MI->removeOperand(SrcOpIdx);
if (MI->getNumOperands() == 1)
MI->eraseFromParent();
}
@@ -494,15 +494,15 @@ void TailDuplicator::updateSuccessorsPHIs(
for (unsigned i = MI.getNumOperands() - 2; i != Idx; i -= 2) {
MachineOperand &MO = MI.getOperand(i + 1);
if (MO.getMBB() == FromBB) {
- MI.RemoveOperand(i + 1);
- MI.RemoveOperand(i);
+ MI.removeOperand(i + 1);
+ MI.removeOperand(i);
}
}
} else
Idx = 0;
// If Idx is set, the operands at Idx and Idx+1 must be removed.
- // We reuse the location to avoid expensive RemoveOperand calls.
+ // We reuse the location to avoid expensive removeOperand calls.
DenseMap<Register, AvailableValsTy>::iterator LI =
SSAUpdateVals.find(Reg);
@@ -539,8 +539,8 @@ void TailDuplicator::updateSuccessorsPHIs(
}
}
if (Idx != 0) {
- MI.RemoveOperand(Idx + 1);
- MI.RemoveOperand(Idx);
+ MI.removeOperand(Idx + 1);
+ MI.removeOperand(Idx);
}
}
}
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 223ff9be5f0cc..bebb35e1204bb 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -1731,11 +1731,11 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
// From %reg = INSERT_SUBREG %reg, %subreg, subidx
// To %reg:subidx = COPY %subreg
unsigned SubIdx = mi->getOperand(3).getImm();
- mi->RemoveOperand(3);
+ mi->removeOperand(3);
assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
mi->getOperand(0).setSubReg(SubIdx);
mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
- mi->RemoveOperand(1);
+ mi->removeOperand(1);
mi->setDesc(TII->get(TargetOpcode::COPY));
LLVM_DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
@@ -1856,7 +1856,7 @@ eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
LLVM_DEBUG(dbgs() << "Turned: " << MI << " into an IMPLICIT_DEF");
MI.setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
for (int j = MI.getNumOperands() - 1, ee = 0; j > ee; --j)
- MI.RemoveOperand(j);
+ MI.removeOperand(j);
} else {
if (LIS)
LIS->RemoveMachineInstrFromMaps(MI);
diff --git a/llvm/lib/CodeGen/UnreachableBlockElim.cpp b/llvm/lib/CodeGen/UnreachableBlockElim.cpp
index 55b0e7d89558a..5e8514f525e9d 100644
--- a/llvm/lib/CodeGen/UnreachableBlockElim.cpp
+++ b/llvm/lib/CodeGen/UnreachableBlockElim.cpp
@@ -125,8 +125,8 @@ bool UnreachableMachineBlockElim::runOnMachineFunction(MachineFunction &F) {
for (unsigned i = start->getNumOperands() - 1; i >= 2; i-=2)
if (start->getOperand(i).isMBB() &&
start->getOperand(i).getMBB() == &BB) {
- start->RemoveOperand(i);
- start->RemoveOperand(i-1);
+ start->removeOperand(i);
+ start->removeOperand(i-1);
}
start++;
@@ -156,8 +156,8 @@ bool UnreachableMachineBlockElim::runOnMachineFunction(MachineFunction &F) {
while (phi != BB.end() && phi->isPHI()) {
for (unsigned i = phi->getNumOperands() - 1; i >= 2; i-=2)
if (!preds.count(phi->getOperand(i).getMBB())) {
- phi->RemoveOperand(i);
- phi->RemoveOperand(i-1);
+ phi->removeOperand(i);
+ phi->removeOperand(i-1);
ModifiedPHI = true;
}
diff --git a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
index 82e8df3b73f90..343f888b7552e 100644
--- a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
@@ -247,8 +247,8 @@ void SSACCmpConv::updateTailPHIs() {
for (unsigned oi = I.getNumOperands(); oi > 2; oi -= 2) {
// PHI operands are (Reg, MBB) at (oi-2, oi-1).
if (I.getOperand(oi - 1).getMBB() == CmpBB) {
- I.RemoveOperand(oi - 1);
- I.RemoveOperand(oi - 2);
+ I.removeOperand(oi - 1);
+ I.removeOperand(oi - 2);
}
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 74a2b7d9a3a86..8414a1f86b1a9 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -1438,7 +1438,7 @@ bool AArch64InstrInfo::optimizeCompareInstr(
return false;
const MCInstrDesc &MCID = get(NewOpc);
CmpInstr.setDesc(MCID);
- CmpInstr.RemoveOperand(DeadNZCVIdx);
+ CmpInstr.removeOperand(DeadNZCVIdx);
bool succeeded = UpdateOperandRegClass(CmpInstr);
(void)succeeded;
assert(succeeded && "Some operands reg class are incompatible!");
diff --git a/llvm/lib/Target/AArch64/AArch64SLSHardening.cpp b/llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
index c4965e7146ff4..364ce687fd554 100644
--- a/llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
+++ b/llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
@@ -360,8 +360,8 @@ AArch64SLSHardening::ConvertBLRToBL(MachineBasicBlock &MBB,
assert(ImpSPOpIdx != -1);
int FirstOpIdxToRemove = std::max(ImpLROpIdx, ImpSPOpIdx);
int SecondOpIdxToRemove = std::min(ImpLROpIdx, ImpSPOpIdx);
- BL->RemoveOperand(FirstOpIdxToRemove);
- BL->RemoveOperand(SecondOpIdxToRemove);
+ BL->removeOperand(FirstOpIdxToRemove);
+ BL->removeOperand(SecondOpIdxToRemove);
// Now copy over the implicit operands from the original BLR
BL->copyImplicitOps(MF, BLR);
MF.moveCallSiteInfo(&BLR, BL);
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
index 8d92169ac7f70..2ed233bc9ebd1 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
@@ -260,7 +260,7 @@ void applyFoldMergeToZext(MachineInstr &MI, MachineRegisterInfo &MRI,
// %d(s64) = G_ZEXT %a(s32)
Observer.changingInstr(MI);
MI.setDesc(B.getTII().get(TargetOpcode::G_ZEXT));
- MI.RemoveOperand(2);
+ MI.removeOperand(2);
Observer.changedInstr(MI);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
index cc45c6642ac54..ce6f15a799b72 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
@@ -149,7 +149,7 @@ bool AArch64PostSelectOptimize::optimizeNZCVDefs(MachineBasicBlock &MBB) {
"op in fcmp range: "
<< II);
II.setDesc(TII->get(NewOpc));
- II.RemoveOperand(DeadNZCVIdx);
+ II.removeOperand(DeadNZCVIdx);
// Changing the opcode can result in
diff ering regclass requirements,
// e.g. SUBSWri uses gpr32 for the dest, whereas SUBWri uses gpr32sp.
// Constrain the regclasses, possibly introducing a copy.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 3382bcf00ff58..2abc20fa5b65e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -92,7 +92,7 @@ bool AMDGPUInstructionSelector::isVCC(Register Reg,
bool AMDGPUInstructionSelector::constrainCopyLikeIntrin(MachineInstr &MI,
unsigned NewOpc) const {
MI.setDesc(TII.get(NewOpc));
- MI.RemoveOperand(1); // Remove intrinsic ID.
+ MI.removeOperand(1); // Remove intrinsic ID.
MI.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
MachineOperand &Dst = MI.getOperand(0);
@@ -631,7 +631,7 @@ bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR_TRUNC(
MachineInstr *Src1Def = getDefIgnoringCopies(Src1, *MRI);
if (Src1Def && Src1Def->getOpcode() == AMDGPU::G_IMPLICIT_DEF) {
MI.setDesc(TII.get(AMDGPU::COPY));
- MI.RemoveOperand(2);
+ MI.removeOperand(2);
return RBI.constrainGenericRegister(Dst, AMDGPU::SReg_32RegClass, *MRI) &&
RBI.constrainGenericRegister(Src0, AMDGPU::SReg_32RegClass, *MRI);
}
@@ -3108,7 +3108,7 @@ bool AMDGPUInstructionSelector::selectGlobalAtomicFadd(
bool AMDGPUInstructionSelector::selectBVHIntrinsic(MachineInstr &MI) const{
MI.setDesc(TII.get(MI.getOperand(1).getImm()));
- MI.RemoveOperand(1);
+ MI.removeOperand(1);
MI.addImplicitDefUseOperands(*MI.getParent()->getParent());
return true;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 1a0ebc4c8fe20..07c28e25467a8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -3708,9 +3708,9 @@ bool AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper,
// The remaining operands were used to set fields in the MemOperand on
// construction.
for (int I = 6; I > 3; --I)
- MI.RemoveOperand(I);
+ MI.removeOperand(I);
- MI.RemoveOperand(1); // Remove the intrinsic ID.
+ MI.removeOperand(1); // Remove the intrinsic ID.
Observer.changedInstr(MI);
return true;
}
@@ -4627,7 +4627,7 @@ bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
return false;
// TODO: Make sure the TFE operand bit is set.
- MI.RemoveOperand(1);
+ MI.removeOperand(1);
// Handle the easy case that requires no repack instructions.
if (Ty == S32) {
@@ -4757,7 +4757,7 @@ bool AMDGPULegalizerInfo::legalizeSBufferLoad(
// should be fixed to have a memory operand. Since it's readnone, we're not
// allowed to add one.
MI.setDesc(B.getTII().get(AMDGPU::G_AMDGPU_S_BUFFER_LOAD));
- MI.RemoveOperand(1); // Remove intrinsic ID
+ MI.removeOperand(1); // Remove intrinsic ID
// FIXME: When intrinsic definition is fixed, this should have an MMO already.
// TODO: Should this use datalayout alignment?
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 7dac64d0808a8..8f8ed936422d1 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -291,7 +291,7 @@ static bool updateOperand(FoldCandidate &Fold,
// when looking at a use.
Dst0.setReg(NewReg0);
for (unsigned I = MI->getNumOperands() - 1; I > 0; --I)
- MI->RemoveOperand(I);
+ MI->removeOperand(I);
MI->setDesc(TII.get(AMDGPU::IMPLICIT_DEF));
if (Fold.isCommuted())
@@ -745,7 +745,7 @@ void SIFoldOperands::foldOperand(
while (ImpOpI != ImpOpE) {
MachineInstr::mop_iterator Tmp = ImpOpI;
ImpOpI++;
- UseMI->RemoveOperand(UseMI->getOperandNo(Tmp));
+ UseMI->removeOperand(UseMI->getOperandNo(Tmp));
}
CopiesToReplace.push_back(UseMI);
} else {
@@ -774,7 +774,7 @@ void SIFoldOperands::foldOperand(
UseMI->setDesc(TII->get(AMDGPU::REG_SEQUENCE));
for (unsigned I = UseMI->getNumOperands() - 1; I > 0; --I)
- UseMI->RemoveOperand(I);
+ UseMI->removeOperand(I);
MachineInstrBuilder B(*MBB.getParent(), UseMI);
DenseMap<TargetInstrInfo::RegSubRegPair, Register> VGPRCopies;
@@ -877,7 +877,7 @@ void SIFoldOperands::foldOperand(
UseMI->getOperand(1).ChangeToImmediate(OpToFold.getImm());
else
UseMI->getOperand(1).ChangeToFrameIndex(OpToFold.getIndex());
- UseMI->RemoveOperand(2); // Remove exec read (or src1 for readlane)
+ UseMI->removeOperand(2); // Remove exec read (or src1 for readlane)
return;
}
@@ -896,7 +896,7 @@ void SIFoldOperands::foldOperand(
UseMI->getOperand(1).setReg(OpToFold.getReg());
UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());
UseMI->getOperand(1).setIsKill(false);
- UseMI->RemoveOperand(2); // Remove exec read (or src1 for readlane)
+ UseMI->removeOperand(2); // Remove exec read (or src1 for readlane)
return;
}
}
@@ -1031,7 +1031,7 @@ static void stripExtraCopyOperands(MachineInstr &MI) {
Desc.getNumImplicitDefs();
for (unsigned I = MI.getNumOperands() - 1; I >= NumOps; --I)
- MI.RemoveOperand(I);
+ MI.removeOperand(I);
}
static void mutateCopyOp(MachineInstr &MI, const MCInstrDesc &NewDesc) {
@@ -1099,7 +1099,7 @@ static bool tryConstantFoldOp(MachineRegisterInfo &MRI, const SIInstrInfo *TII,
// Be careful to change the right operand, src0 may belong to a
diff erent
// instruction.
MI->getOperand(Src0Idx).ChangeToImmediate(NewImm);
- MI->RemoveOperand(Src1Idx);
+ MI->removeOperand(Src1Idx);
mutateCopyOp(*MI, TII->get(getMovOpc(IsSGPR)));
return true;
}
@@ -1118,11 +1118,11 @@ static bool tryConstantFoldOp(MachineRegisterInfo &MRI, const SIInstrInfo *TII,
Opc == AMDGPU::S_OR_B32) {
if (Src1Val == 0) {
// y = or x, 0 => y = copy x
- MI->RemoveOperand(Src1Idx);
+ MI->removeOperand(Src1Idx);
mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
} else if (Src1Val == -1) {
// y = or x, -1 => y = v_mov_b32 -1
- MI->RemoveOperand(Src1Idx);
+ MI->removeOperand(Src1Idx);
mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_OR_B32)));
} else
return false;
@@ -1135,11 +1135,11 @@ static bool tryConstantFoldOp(MachineRegisterInfo &MRI, const SIInstrInfo *TII,
MI->getOpcode() == AMDGPU::S_AND_B32) {
if (Src1Val == 0) {
// y = and x, 0 => y = v_mov_b32 0
- MI->RemoveOperand(Src0Idx);
+ MI->removeOperand(Src0Idx);
mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_AND_B32)));
} else if (Src1Val == -1) {
// y = and x, -1 => y = copy x
- MI->RemoveOperand(Src1Idx);
+ MI->removeOperand(Src1Idx);
mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
stripExtraCopyOperands(*MI);
} else
@@ -1153,7 +1153,7 @@ static bool tryConstantFoldOp(MachineRegisterInfo &MRI, const SIInstrInfo *TII,
MI->getOpcode() == AMDGPU::S_XOR_B32) {
if (Src1Val == 0) {
// y = xor x, 0 => y = copy x
- MI->RemoveOperand(Src1Idx);
+ MI->removeOperand(Src1Idx);
mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
return true;
}
@@ -1191,12 +1191,12 @@ bool SIFoldOperands::tryFoldCndMask(MachineInstr &MI) const {
TII->get(Src0->isReg() ? (unsigned)AMDGPU::COPY : getMovOpc(false));
int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
if (Src2Idx != -1)
- MI.RemoveOperand(Src2Idx);
- MI.RemoveOperand(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1));
+ MI.removeOperand(Src2Idx);
+ MI.removeOperand(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1));
if (Src1ModIdx != -1)
- MI.RemoveOperand(Src1ModIdx);
+ MI.removeOperand(Src1ModIdx);
if (Src0ModIdx != -1)
- MI.RemoveOperand(Src0ModIdx);
+ MI.removeOperand(Src0ModIdx);
mutateCopyOp(MI, NewDesc);
LLVM_DEBUG(dbgs() << MI);
return true;
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index a282900c59833..6601c12488f08 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -11645,7 +11645,7 @@ void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
MachineOperand &CPol = MI.getOperand(CPolIdx);
CPol.setImm(CPol.getImm() & ~AMDGPU::CPol::GLC);
}
- MI.RemoveOperand(0);
+ MI.removeOperand(0);
MI.setDesc(TII->get(NoRetAtomicOp));
return;
}
@@ -11664,7 +11664,7 @@ void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
// Change this into a noret atomic.
MI.setDesc(TII->get(NoRetAtomicOp));
- MI.RemoveOperand(0);
+ MI.removeOperand(0);
// If we only remove the def operand from the atomic instruction, the
// extract_subreg will be left with a use of a vreg without a def.
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index b2c54db697107..8b79e1c8f087d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2901,9 +2901,9 @@ static void removeModOperands(MachineInstr &MI) {
int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
AMDGPU::OpName::src2_modifiers);
- MI.RemoveOperand(Src2ModIdx);
- MI.RemoveOperand(Src1ModIdx);
- MI.RemoveOperand(Src0ModIdx);
+ MI.removeOperand(Src2ModIdx);
+ MI.removeOperand(Src1ModIdx);
+ MI.removeOperand(Src0ModIdx);
}
bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
@@ -3017,9 +3017,9 @@ bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
// instead of having to modify in place.
// Remove these first since they are at the end.
- UseMI.RemoveOperand(
+ UseMI.removeOperand(
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod));
- UseMI.RemoveOperand(
+ UseMI.removeOperand(
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp));
Register Src1Reg = Src1->getReg();
@@ -3100,9 +3100,9 @@ bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
// instead of having to modify in place.
// Remove these first since they are at the end.
- UseMI.RemoveOperand(
+ UseMI.removeOperand(
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod));
- UseMI.RemoveOperand(
+ UseMI.removeOperand(
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp));
if (Opc == AMDGPU::V_MAC_F32_e64 ||
@@ -3356,7 +3356,7 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
// We cannot just remove the DefMI here, calling pass will crash.
DefMI->setDesc(get(AMDGPU::IMPLICIT_DEF));
for (unsigned I = DefMI->getNumOperands() - 1; I != 0; --I)
- DefMI->RemoveOperand(I);
+ DefMI->removeOperand(I);
};
int64_t Imm;
@@ -4906,7 +4906,7 @@ MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
void SIInstrInfo::swapOperands(MachineInstr &Inst) const {
assert(Inst.getNumExplicitOperands() == 3);
MachineOperand Op1 = Inst.getOperand(1);
- Inst.RemoveOperand(1);
+ Inst.removeOperand(1);
Inst.addOperand(Op1);
}
@@ -5348,7 +5348,7 @@ bool SIInstrInfo::moveFlatAddrToVGPR(MachineInstr &Inst) const {
// Clear use list from the old vaddr holding a zero register.
MRI.removeRegOperandFromUseList(&NewVAddr);
MRI.moveOperands(&NewVAddr, &SAddr, 1);
- Inst.RemoveOperand(OldSAddrIdx);
+ Inst.removeOperand(OldSAddrIdx);
// Update the use list with the pointer we have just moved from vaddr to
// saddr position. Otherwise new vaddr will be missing from the use list.
MRI.removeRegOperandFromUseList(&NewVAddr);
@@ -5360,14 +5360,14 @@ bool SIInstrInfo::moveFlatAddrToVGPR(MachineInstr &Inst) const {
int NewVDstIn = AMDGPU::getNamedOperandIdx(NewOpc,
AMDGPU::OpName::vdst_in);
- // RemoveOperand doesn't try to fixup tied operand indexes at it goes, so
+ // removeOperand doesn't try to fixup tied operand indexes at it goes, so
// it asserts. Untie the operands for now and retie them afterwards.
if (NewVDstIn != -1) {
int OldVDstIn = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in);
Inst.untieRegOperand(OldVDstIn);
}
- Inst.RemoveOperand(OldVAddrIdx);
+ Inst.removeOperand(OldVAddrIdx);
if (NewVDstIn != -1) {
int NewVDst = AMDGPU::getNamedOperandIdx(NewOpc, AMDGPU::OpName::vdst);
@@ -6159,7 +6159,7 @@ MachineBasicBlock *SIInstrInfo::moveToVALU(MachineInstr &TopInst,
BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(Opc), VCC)
.addReg(EXEC)
.addReg(IsSCC ? VCC : CondReg);
- Inst.RemoveOperand(1);
+ Inst.removeOperand(1);
}
break;
@@ -6326,7 +6326,7 @@ MachineBasicBlock *SIInstrInfo::moveToVALU(MachineInstr &TopInst,
addSCCDefUsersToVALUWorklist(Op, Inst, Worklist);
if (Op.isUse())
addSCCDefsToVALUWorklist(Op, Worklist);
- Inst.RemoveOperand(i);
+ Inst.removeOperand(i);
}
}
@@ -6356,7 +6356,7 @@ MachineBasicBlock *SIInstrInfo::moveToVALU(MachineInstr &TopInst,
uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
- Inst.RemoveOperand(2); // Remove old immediate.
+ Inst.removeOperand(2); // Remove old immediate.
Inst.addOperand(MachineOperand::CreateImm(Offset));
Inst.addOperand(MachineOperand::CreateImm(BitWidth));
}
@@ -6390,7 +6390,7 @@ MachineBasicBlock *SIInstrInfo::moveToVALU(MachineInstr &TopInst,
// these are deleted later, but at -O0 it would leave a suspicious
// looking illegal copy of an undef register.
for (unsigned I = Inst.getNumOperands() - 1; I != 0; --I)
- Inst.RemoveOperand(I);
+ Inst.removeOperand(I);
Inst.setDesc(get(AMDGPU::IMPLICIT_DEF));
continue;
}
@@ -6432,7 +6432,7 @@ SIInstrInfo::moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
AMDGPU::V_ADD_U32_e64 : AMDGPU::V_SUB_U32_e64;
assert(Inst.getOperand(3).getReg() == AMDGPU::SCC);
- Inst.RemoveOperand(3);
+ Inst.removeOperand(3);
Inst.setDesc(get(NewOpc));
Inst.addOperand(MachineOperand::CreateImm(0)); // clamp bit
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
index 66518fbbe4fbf..f37314619a985 100644
--- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -573,7 +573,7 @@ void SILowerControlFlow::combineMasks(MachineInstr &MI) {
else return;
Register Reg = MI.getOperand(OpToReplace).getReg();
- MI.RemoveOperand(OpToReplace);
+ MI.removeOperand(OpToReplace);
MI.addOperand(Ops[UniqueOpndIdx]);
if (MRI->use_empty(Reg))
MRI->getUniqueVRegDef(Reg)->eraseFromParent();
diff --git a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
index 49295b1f06701..8d33b8a1fd4b2 100644
--- a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
@@ -235,7 +235,7 @@ bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) const {
TII->get(IsVCCZ ? AMDGPU::S_CBRANCH_EXECZ : AMDGPU::S_CBRANCH_EXECNZ));
}
- MI.RemoveOperand(MI.findRegisterUseOperandIdx(CondReg, false /*Kill*/, TRI));
+ MI.removeOperand(MI.findRegisterUseOperandIdx(CondReg, false /*Kill*/, TRI));
MI.addImplicitDefUseOperands(*MBB.getParent());
return true;
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index d853408bc71f3..b8d0e0370f0fb 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -2157,7 +2157,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
}
if (NewOpc != -1) {
- MI->RemoveOperand(
+ MI->removeOperand(
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr));
MI->setDesc(TII->get(NewOpc));
return;
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index 07b1c42a9b2fc..e437552c2afdc 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -297,7 +297,7 @@ void SIShrinkInstructions::shrinkMIMG(MachineInstr &MI) {
MI.getOperand(VAddr0Idx).setIsKill(IsKill);
for (unsigned i = 1; i < Info->VAddrDwords; ++i)
- MI.RemoveOperand(VAddr0Idx + 1);
+ MI.removeOperand(VAddr0Idx + 1);
if (ToUntie >= 0) {
MI.tieOperands(
@@ -564,7 +564,7 @@ static MachineInstr* matchSwap(MachineInstr &MovT, MachineRegisterInfo &MRI,
.addReg(X1.Reg, 0, X1.SubReg).getInstr();
if (MovX->hasRegisterImplicitUseOperand(AMDGPU::EXEC)) {
// Drop implicit EXEC.
- MIB->RemoveOperand(MIB->getNumExplicitOperands());
+ MIB->removeOperand(MIB->getNumExplicitOperands());
MIB->copyImplicitOps(*MBB.getParent(), *MovX);
}
}
@@ -580,7 +580,7 @@ static MachineInstr* matchSwap(MachineInstr &MovT, MachineRegisterInfo &MRI,
unsigned OpNo = MovT.getNumExplicitOperands() + I;
const MachineOperand &Op = MovT.getOperand(OpNo);
if (Op.isKill() && TRI.regsOverlap(X, Op.getReg()))
- MovT.RemoveOperand(OpNo);
+ MovT.removeOperand(OpNo);
}
}
diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
index efc480e79aa6c..6a6987942b0f3 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
@@ -1453,7 +1453,7 @@ void SIWholeQuadMode::lowerCopyInstrs() {
}
int Index = MI->findRegisterUseOperandIdx(AMDGPU::EXEC);
while (Index >= 0) {
- MI->RemoveOperand(Index);
+ MI->removeOperand(Index);
Index = MI->findRegisterUseOperandIdx(AMDGPU::EXEC);
}
MI->setDesc(TII->get(AMDGPU::COPY));
@@ -1468,7 +1468,7 @@ void SIWholeQuadMode::lowerCopyInstrs() {
// an undef input so it is being replaced by a simple copy.
// There should be a second undef source that we should remove.
assert(MI->getOperand(2).isUndef());
- MI->RemoveOperand(2);
+ MI->removeOperand(2);
MI->untieRegOperand(1);
} else {
assert(MI->getNumExplicitOperands() == 2);
diff --git a/llvm/lib/Target/ARC/ARCOptAddrMode.cpp b/llvm/lib/Target/ARC/ARCOptAddrMode.cpp
index c956f00b628d7..27a9bca7488f6 100644
--- a/llvm/lib/Target/ARC/ARCOptAddrMode.cpp
+++ b/llvm/lib/Target/ARC/ARCOptAddrMode.cpp
@@ -459,12 +459,12 @@ void ARCOptAddrMode::changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
Register BaseReg = Ldst.getOperand(BasePos).getReg();
- Ldst.RemoveOperand(OffPos);
- Ldst.RemoveOperand(BasePos);
+ Ldst.removeOperand(OffPos);
+ Ldst.removeOperand(BasePos);
if (IsStore) {
Src = Ldst.getOperand(BasePos - 1);
- Ldst.RemoveOperand(BasePos - 1);
+ Ldst.removeOperand(BasePos - 1);
}
Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode));
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index bac68183b7af1..9bb9df536b2ee 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1703,7 +1703,7 @@ bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
// or some other super-register.
int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD);
if (ImpDefIdx != -1)
- MI.RemoveOperand(ImpDefIdx);
+ MI.removeOperand(ImpDefIdx);
// Change the opcode and operands.
MI.setDesc(get(ARM::VMOVD));
@@ -2598,7 +2598,7 @@ bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
// ahead: strip all existing registers off and add them back again
// in the right order.
for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
- MI->RemoveOperand(i);
+ MI->removeOperand(i);
// Add the complete list back in.
MachineInstrBuilder MIB(MF, &*MI);
@@ -2626,7 +2626,7 @@ bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
// Turn it into a move.
MI.setDesc(TII.get(ARM::MOVr));
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
- MI.RemoveOperand(FrameRegIdx+1);
+ MI.removeOperand(FrameRegIdx+1);
Offset = 0;
return true;
} else if (Offset < 0) {
@@ -5103,7 +5103,7 @@ void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
SrcReg = MI.getOperand(1).getReg();
for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
- MI.RemoveOperand(i - 1);
+ MI.removeOperand(i - 1);
// Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
MI.setDesc(get(ARM::VORRd));
@@ -5122,7 +5122,7 @@ void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
SrcReg = MI.getOperand(1).getReg();
for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
- MI.RemoveOperand(i - 1);
+ MI.removeOperand(i - 1);
DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
@@ -5155,7 +5155,7 @@ void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
break;
for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
- MI.RemoveOperand(i - 1);
+ MI.removeOperand(i - 1);
// Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
// Again DDst may be undefined at the beginning of this instruction.
@@ -5190,7 +5190,7 @@ void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
break;
for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
- MI.RemoveOperand(i - 1);
+ MI.removeOperand(i - 1);
if (DSrc == DDst) {
// Destination can be:
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index f0fc308410125..987b67fcae485 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -12178,7 +12178,7 @@ void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
if (Subtarget->isThumb1Only()) {
for (unsigned c = MCID->getNumOperands() - 4; c--;) {
MI.addOperand(MI.getOperand(1));
- MI.RemoveOperand(1);
+ MI.removeOperand(1);
}
// Restore the ties
@@ -12216,7 +12216,7 @@ void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
definesCPSR = true;
if (MO.isDead())
deadCPSR = true;
- MI.RemoveOperand(i);
+ MI.removeOperand(i);
break;
}
}
diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
index 188b5562cac93..daf0656e89626 100644
--- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -733,7 +733,7 @@ bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB,
// Add the offset to the SB register.
MIB->setDesc(TII.get(Opcodes.ADDrr));
- MIB->RemoveOperand(1);
+ MIB->removeOperand(1);
MIB.addReg(ARM::R9) // FIXME: don't hardcode R9
.addReg(Offset)
.add(predOps(ARMCC::AL))
@@ -748,7 +748,7 @@ bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB,
} else {
// Load the global's address from the constant pool.
MIB->setDesc(TII.get(Opcodes.ConstPoolLoad));
- MIB->RemoveOperand(1);
+ MIB->removeOperand(1);
addOpsForConstantPoolLoad(MIB, GV, /*IsSBREL*/ false);
}
} else if (STI.isTargetMachO()) {
@@ -997,7 +997,7 @@ bool ARMInstructionSelector::select(MachineInstr &I) {
auto CPIndex =
ConstPool->getConstantPoolIndex(I.getOperand(1).getFPImm(), Alignment);
MIB->setDesc(TII.get(LoadOpcode));
- MIB->RemoveOperand(1);
+ MIB->removeOperand(1);
MIB.addConstantPoolIndex(CPIndex, /*Offset*/ 0, /*TargetFlags*/ 0)
.addMemOperand(
MF.getMachineMemOperand(MachinePointerInfo::getConstantPool(MF),
diff --git a/llvm/lib/Target/ARM/ARMSLSHardening.cpp b/llvm/lib/Target/ARM/ARMSLSHardening.cpp
index 332acb4531240..fa80b75484e19 100644
--- a/llvm/lib/Target/ARM/ARMSLSHardening.cpp
+++ b/llvm/lib/Target/ARM/ARMSLSHardening.cpp
@@ -322,8 +322,8 @@ MachineBasicBlock &ARMSLSHardening::ConvertIndirectCallToIndirectJump(
assert(ImpSPOpIdx != -1);
int FirstOpIdxToRemove = std::max(ImpLROpIdx, ImpSPOpIdx);
int SecondOpIdxToRemove = std::min(ImpLROpIdx, ImpSPOpIdx);
- BL->RemoveOperand(FirstOpIdxToRemove);
- BL->RemoveOperand(SecondOpIdxToRemove);
+ BL->removeOperand(FirstOpIdxToRemove);
+ BL->removeOperand(SecondOpIdxToRemove);
// Now copy over the implicit operands from the original IndirectCall
BL->copyImplicitOps(MF, IndirectCall);
MF.moveCallSiteInfo(&IndirectCall, BL);
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index ebd139af22190..60dbc7b920132 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -555,7 +555,7 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
MI.setDesc(TII.get(ARM::tMOVr));
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
// Remove offset and remaining explicit predicate operands.
- do MI.RemoveOperand(FrameRegIdx+1);
+ do MI.removeOperand(FrameRegIdx+1);
while (MI.getNumOperands() > FrameRegIdx+1);
MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
MIB.add(predOps(ARMCC::AL));
@@ -592,7 +592,7 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
// Remove the cc_out operand.
if (HasCCOut)
- MI.RemoveOperand(MI.getNumOperands()-1);
+ MI.removeOperand(MI.getNumOperands()-1);
Offset = 0;
return true;
}
@@ -626,7 +626,7 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
return Offset == 0;
}
- MI.RemoveOperand(FrameRegIdx+1);
+ MI.removeOperand(FrameRegIdx+1);
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
NewOpc = immediateOffsetOpcode(Opcode);
AddrMode = ARMII::AddrModeT2_i12;
diff --git a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
index d5c0f3f608ec9..f76ff10f6216e 100644
--- a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
@@ -338,7 +338,7 @@ void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
static void removeOperands(MachineInstr &MI, unsigned i) {
unsigned Op = i;
for (unsigned e = MI.getNumOperands(); i != e; ++i)
- MI.RemoveOperand(Op);
+ MI.removeOperand(Op);
}
/// convertToNonSPOpcode - Change the opcode to the non-SP version, because
diff --git a/llvm/lib/Target/AVR/AVRRegisterInfo.cpp b/llvm/lib/Target/AVR/AVRRegisterInfo.cpp
index 048509546e91c..c34cf7480ae59 100644
--- a/llvm/lib/Target/AVR/AVRRegisterInfo.cpp
+++ b/llvm/lib/Target/AVR/AVRRegisterInfo.cpp
@@ -152,7 +152,7 @@ void AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
if (MI.getOpcode() == AVR::FRMIDX) {
MI.setDesc(TII.get(AVR::MOVWRdRr));
MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
- MI.RemoveOperand(2);
+ MI.removeOperand(2);
assert(Offset > 0 && "Invalid offset");
diff --git a/llvm/lib/Target/CSKY/CSKYRegisterInfo.cpp b/llvm/lib/Target/CSKY/CSKYRegisterInfo.cpp
index 1335bb6aa4c73..f811c834c260a 100644
--- a/llvm/lib/Target/CSKY/CSKYRegisterInfo.cpp
+++ b/llvm/lib/Target/CSKY/CSKYRegisterInfo.cpp
@@ -282,7 +282,7 @@ void CSKYRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MI->setDesc(TII->get(TargetOpcode::COPY));
MI->getOperand(FIOperandNum)
.ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
- MI->RemoveOperand(FIOperandNum + 1);
+ MI->removeOperand(FIOperandNum + 1);
} else {
MI->getOperand(FIOperandNum)
.ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index b2a842233bb86..5f1b156bffda6 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1997,7 +1997,7 @@ bool BitSimplification::genStoreImmediate(MachineInstr *MI) {
if (!isInt<8>(V))
return false;
- MI->RemoveOperand(2);
+ MI->removeOperand(2);
switch (Opc) {
case Hexagon::S2_storerb_io:
MI->setDesc(HII.get(Hexagon::S4_storeirb_io));
diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
index 105bf2811a20c..87799171bea97 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
@@ -868,8 +868,8 @@ void MachineConstPropagator::removeCFGEdge(MachineBasicBlock *From,
int N = PN.getNumOperands() - 2;
while (N > 0) {
if (PN.getOperand(N + 1).getMBB() == From) {
- PN.RemoveOperand(N + 1);
- PN.RemoveOperand(N);
+ PN.removeOperand(N + 1);
+ PN.removeOperand(N);
}
N -= 2;
}
@@ -2510,7 +2510,7 @@ APInt HexagonConstEvaluator::getCmpImm(unsigned Opc, unsigned OpX,
void HexagonConstEvaluator::replaceWithNop(MachineInstr &MI) {
MI.setDesc(HII.get(Hexagon::A2_nop));
while (MI.getNumOperands() > 0)
- MI.RemoveOperand(0);
+ MI.removeOperand(0);
}
bool HexagonConstEvaluator::evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH,
@@ -3165,7 +3165,7 @@ bool HexagonConstEvaluator::rewriteHexBranch(MachineInstr &BrI,
.addMBB(TargetB);
BrI.setDesc(JD);
while (BrI.getNumOperands() > 0)
- BrI.RemoveOperand(0);
+ BrI.removeOperand(0);
// This ensures that all implicit operands (e.g. implicit-def %r31, etc)
// are present in the rewritten branch.
for (auto &Op : NI->operands())
diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
index 2207925ceebaa..f7227dca3b603 100644
--- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
@@ -826,8 +826,8 @@ void HexagonEarlyIfConversion::updatePhiNodes(MachineBasicBlock *WhereB,
FR = RO.getReg(), FSR = RO.getSubReg();
else
continue;
- PN->RemoveOperand(i+1);
- PN->RemoveOperand(i);
+ PN->removeOperand(i+1);
+ PN->removeOperand(i);
}
if (TR == 0)
TR = SR, TSR = SSR;
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index 2693940bb1e97..853553f57ba44 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -696,7 +696,7 @@ bool HexagonExpandCondsets::split(MachineInstr &MI,
MI.setDesc(HII->get(TargetOpcode::COPY));
unsigned S = getRegState(ST);
while (MI.getNumOperands() > 1)
- MI.RemoveOperand(MI.getNumOperands()-1);
+ MI.removeOperand(MI.getNumOperands()-1);
MachineFunction &MF = *MI.getParent()->getParent();
MachineInstrBuilder(MF, MI).addReg(RT.Reg, S, RT.Sub);
return true;
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index 43afae441457a..e93347435eacb 100644
--- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -1911,8 +1911,8 @@ MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop(
for (int i = PN->getNumOperands()-2; i > 0; i -= 2) {
MachineBasicBlock *PredB = PN->getOperand(i+1).getMBB();
if (PredB != Latch) {
- PN->RemoveOperand(i+1);
- PN->RemoveOperand(i);
+ PN->removeOperand(i+1);
+ PN->removeOperand(i);
}
}
PN->addOperand(MachineOperand::CreateReg(NewPR, false));
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 2e80273060d07..b40b63d011f34 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -1662,7 +1662,7 @@ bool HexagonInstrInfo::PredicateInstruction(
MI.setDesc(get(PredOpc));
while (unsigned n = MI.getNumOperands())
- MI.RemoveOperand(n-1);
+ MI.removeOperand(n-1);
for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
MI.addOperand(T->getOperand(i));
diff --git a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
index 1ff248200572e..d2ca03747b263 100644
--- a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
@@ -208,14 +208,14 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
// Try to find in the map.
if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
// Change the 1st operand.
- MI.RemoveOperand(1);
+ MI.removeOperand(1);
MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
} else {
DenseMap<unsigned, std::pair<unsigned, unsigned> >::iterator DI =
PeepholeDoubleRegsMap.find(SrcReg);
if (DI != PeepholeDoubleRegsMap.end()) {
std::pair<unsigned,unsigned> PeepholeSrc = DI->second;
- MI.RemoveOperand(1);
+ MI.removeOperand(1);
MI.addOperand(MachineOperand::CreateReg(
PeepholeSrc.first, false /*isDef*/, false /*isImp*/,
false /*isKill*/, false /*isDead*/, false /*isUndef*/,
diff --git a/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp b/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp
index f26e23befde21..fb6918949cce8 100644
--- a/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp
@@ -201,7 +201,7 @@ void HexagonDCE::removeOperand(NodeAddr<InstrNode*> IA, unsigned OpNum) {
for (NodeAddr<RefNode*> RA : Refs)
OpMap.insert(std::make_pair(RA.Id, getOpNum(RA.Addr->getOp())));
- MI->RemoveOperand(OpNum);
+ MI->removeOperand(OpNum);
for (NodeAddr<RefNode*> RA : Refs) {
unsigned N = OpMap[RA.Id];
diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
index 6e55bc6b5c2cd..f0e56d74fcd11 100644
--- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
@@ -228,7 +228,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
case Hexagon::PS_fia:
MI.setDesc(HII.get(Hexagon::A2_addi));
MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
- MI.RemoveOperand(FIOp+1);
+ MI.removeOperand(FIOp+1);
return;
case Hexagon::PS_fi:
// Set up the instruction for updating below.
diff --git a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
index 4e9a23d077da9..c3ee656e58e26 100644
--- a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
+++ b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
@@ -722,7 +722,7 @@ void MipsBranchExpansion::expandToLongBranch(MBBInfo &I) {
if (I.Br->isUnconditionalBranch()) {
// Change branch destination.
assert(I.Br->getDesc().getNumOperands() == 1);
- I.Br->RemoveOperand(0);
+ I.Br->removeOperand(0);
I.Br->addOperand(MachineOperand::CreateMBB(LongBrMBB));
} else
// Change branch destination and reverse condition.
diff --git a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
index 1efbf55702876..73691e0db3d41 100644
--- a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
+++ b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
@@ -1653,8 +1653,8 @@ void MipsConstantIslands::prescanForConstants() {
I->getOperand(2).ChangeToImmediate(index);
LLVM_DEBUG(dbgs() << "constant island constant " << *I << "\n");
I->setDesc(TII->get(Mips::LwRxPcTcp16));
- I->RemoveOperand(1);
- I->RemoveOperand(1);
+ I->removeOperand(1);
+ I->removeOperand(1);
I->addOperand(MachineOperand::CreateCPI(index, 0));
I->addOperand(MachineOperand::CreateImm(4));
}
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
index 2bf8562895d7f..339dadcec7fee 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
@@ -695,7 +695,7 @@ MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
NewOpc == Mips::JIALC64) {
if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
- MIB->RemoveOperand(0);
+ MIB->removeOperand(0);
for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
MIB.add(I->getOperand(J));
diff --git a/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp b/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
index 2823d300dc6ee..1b5c46c1edba0 100644
--- a/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
+++ b/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
@@ -170,7 +170,7 @@ static void eraseGPOpnd(MachineInstr &MI) {
for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
MachineOperand &MO = MI.getOperand(I);
if (MO.isReg() && MO.getReg() == Reg) {
- MI.RemoveOperand(I);
+ MI.removeOperand(I);
return;
}
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index eada872c2a7db..18cb0c08b0258 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2218,7 +2218,7 @@ bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI,
.addReg(Pred[1].getReg(), RegState::ImplicitDefine);
} else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
- MI.RemoveOperand(0);
+ MI.removeOperand(0);
MI.setDesc(get(PPC::BC));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
@@ -2226,7 +2226,7 @@ bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI,
.addMBB(MBB);
} else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
- MI.RemoveOperand(0);
+ MI.removeOperand(0);
MI.setDesc(get(PPC::BCn));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
@@ -2234,7 +2234,7 @@ bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI,
.addMBB(MBB);
} else {
MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
- MI.RemoveOperand(0);
+ MI.removeOperand(0);
MI.setDesc(get(PPC::BCC));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
@@ -2714,8 +2714,8 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
}
// If we've set the mask, we can transform.
if (Mask != ~0LLU) {
- MI->RemoveOperand(4);
- MI->RemoveOperand(3);
+ MI->removeOperand(4);
+ MI->removeOperand(3);
MI->getOperand(2).setImm(Mask);
NumRcRotatesConvertedToRcAnd++;
}
@@ -2724,7 +2724,7 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
if (MB >= 48) {
uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
NewOpC = PPC::ANDI8_rec;
- MI->RemoveOperand(3);
+ MI->removeOperand(3);
MI->getOperand(2).setImm(Mask);
NumRcRotatesConvertedToRcAnd++;
}
@@ -3026,8 +3026,8 @@ bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
}
case PPC::KILL_PAIR: {
MI.setDesc(get(PPC::UNENCODED_NOP));
- MI.RemoveOperand(1);
- MI.RemoveOperand(0);
+ MI.removeOperand(1);
+ MI.removeOperand(0);
return true;
}
case TargetOpcode::LOAD_STACK_GUARD: {
@@ -3122,7 +3122,7 @@ bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
.addReg(PPC::CR7)
.addImm(1);
MI.setDesc(get(PPC::ISYNC));
- MI.RemoveOperand(0);
+ MI.removeOperand(0);
return true;
}
}
@@ -3188,7 +3188,7 @@ void PPCInstrInfo::replaceInstrOperandWithImm(MachineInstr &MI,
// - implicit reg uses
// Therefore, removing the implicit operand won't change the explicit
// operands layout.
- MI.RemoveOperand(UseOpIdx);
+ MI.removeOperand(UseOpIdx);
}
}
@@ -3199,7 +3199,7 @@ void PPCInstrInfo::replaceInstrWithLI(MachineInstr &MI,
// Remove existing operands.
int OperandToKeep = LII.SetCR ? 1 : 0;
for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
- MI.RemoveOperand(i);
+ MI.removeOperand(i);
// Replace the instruction.
if (LII.SetCR) {
@@ -3790,15 +3790,15 @@ bool PPCInstrInfo::combineRLWINM(MachineInstr &MI,
if (MI.getOpcode() == PPC::RLWINM || MI.getOpcode() == PPC::RLWINM8) {
// Replace MI with "LI 0"
- MI.RemoveOperand(4);
- MI.RemoveOperand(3);
- MI.RemoveOperand(2);
+ MI.removeOperand(4);
+ MI.removeOperand(3);
+ MI.removeOperand(2);
MI.getOperand(1).ChangeToImmediate(0);
MI.setDesc(get(Is64Bit ? PPC::LI8 : PPC::LI));
} else {
// Replace MI with "ANDI_rec reg, 0"
- MI.RemoveOperand(4);
- MI.RemoveOperand(3);
+ MI.removeOperand(4);
+ MI.removeOperand(3);
MI.getOperand(2).setImm(0);
MI.setDesc(get(Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec));
MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
@@ -4282,8 +4282,8 @@ static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
unsigned MinOp = std::min(Op1, Op2);
MachineOperand MOp1 = MI.getOperand(MinOp);
MachineOperand MOp2 = MI.getOperand(MaxOp);
- MI.RemoveOperand(std::max(Op1, Op2));
- MI.RemoveOperand(std::min(Op1, Op2));
+ MI.removeOperand(std::max(Op1, Op2));
+ MI.removeOperand(std::min(Op1, Op2));
// If the operands we are swapping are the two at the end (the common case)
// we can just remove both and add them in the opposite order.
@@ -4297,7 +4297,7 @@ static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops.
for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) {
MOps.push_back(MI.getOperand(i));
- MI.RemoveOperand(i);
+ MI.removeOperand(i);
}
// MOp2 needs to be added next.
MI.addOperand(MOp2);
@@ -4532,8 +4532,8 @@ bool PPCInstrInfo::simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
replaceInstrOperandWithImm(CompareUseMI, 1, 0);
- CompareUseMI.RemoveOperand(3);
- CompareUseMI.RemoveOperand(2);
+ CompareUseMI.removeOperand(3);
+ CompareUseMI.removeOperand(2);
continue;
}
LLVM_DEBUG(
@@ -4542,8 +4542,8 @@ bool PPCInstrInfo::simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
LLVM_DEBUG(dbgs() << "Is converted to:\n");
// Convert to copy and remove unneeded operands.
CompareUseMI.setDesc(get(PPC::COPY));
- CompareUseMI.RemoveOperand(3);
- CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1);
+ CompareUseMI.removeOperand(3);
+ CompareUseMI.removeOperand(RegToCopy == TrueReg ? 2 : 1);
CmpIselsConverted++;
Changed = true;
LLVM_DEBUG(CompareUseMI.dump());
@@ -4887,7 +4887,7 @@ bool PPCInstrInfo::transformToImmFormFedByAdd(
SmallVector<MachineOperand, 2> MOps;
for (unsigned i = MI.getNumOperands() - 1; i >= III.ZeroIsSpecialOrig; i--) {
MOps.push_back(MI.getOperand(i));
- MI.RemoveOperand(i);
+ MI.removeOperand(i);
}
// Remove the last MO in the list, which is ZERO operand in fact.
@@ -5010,7 +5010,7 @@ bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
// just convert this to a COPY. Can't do this post-RA since we've already
// cleaned up the copies.
else if (!SetCR && ShAmt == 0 && !PostRA) {
- MI.RemoveOperand(2);
+ MI.removeOperand(2);
MI.setDesc(get(PPC::COPY));
} else {
// The 32 bit and 64 bit instructions are quite
diff erent.
diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
index 88576d7e63ebc..67d91d23962ce 100644
--- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -986,7 +986,7 @@ bool PPCMIPeephole::simplifyCode() {
LiMI->getOpcode() == PPC::LI8) &&
"Invalid Opcode!");
auto LiImm = LiMI->getOperand(1).getImm(); // save the imm of LI
- LiMI->RemoveOperand(1); // remove the imm of LI
+ LiMI->removeOperand(1); // remove the imm of LI
LiMI->setDesc(TII->get(LiMI->getOpcode() == PPC::LI ? PPC::ADDI
: PPC::ADDI8));
MachineInstrBuilder(*LiMI->getParent()->getParent(), *LiMI)
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 87690e0c92360..ddcee1a0a68bc 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1108,7 +1108,7 @@ void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
MBB.erase(II);
if (SpillsKnownBit && KillsCRBit && !SeenUse) {
Ins->setDesc(TII.get(PPC::UNENCODED_NOP));
- Ins->RemoveOperand(0);
+ Ins->removeOperand(0);
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
index b21fd47cafd36..16e44115c990e 100644
--- a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
@@ -247,7 +247,7 @@ bool RISCVMergeBaseOffsetOpt::detectAndFoldOffset(MachineInstr &HiLUI,
// Update the offsets in global address lowering.
HiLUI.getOperand(1).setOffset(Offset);
// Update the immediate in the Tail instruction to add the offset.
- Tail.RemoveOperand(2);
+ Tail.removeOperand(2);
MachineOperand &ImmOp = LoADDI.getOperand(2);
ImmOp.setOffset(Offset);
Tail.addOperand(ImmOp);
diff --git a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
index 4893acc813352..0df1e2dd99914 100644
--- a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
@@ -224,7 +224,7 @@ bool SystemZElimCompare::convertToBRCT(
// The transformation is OK. Rebuild Branch as a BRCT(G) or BRCTH.
MachineOperand Target(Branch->getOperand(2));
while (Branch->getNumOperands())
- Branch->RemoveOperand(0);
+ Branch->removeOperand(0);
Branch->setDesc(TII->get(BRCT));
MachineInstrBuilder MIB(*Branch->getParent()->getParent(), Branch);
MIB.add(MI.getOperand(0)).add(MI.getOperand(1)).add(Target);
@@ -267,7 +267,7 @@ bool SystemZElimCompare::convertToLoadAndTrap(
// The transformation is OK. Rebuild Branch as a load-and-trap.
while (Branch->getNumOperands())
- Branch->RemoveOperand(0);
+ Branch->removeOperand(0);
Branch->setDesc(TII->get(LATOpcode));
MachineInstrBuilder(*Branch->getParent()->getParent(), Branch)
.add(MI.getOperand(0))
@@ -649,16 +649,16 @@ bool SystemZElimCompare::fuseCompareOperations(
// Clear out all current operands.
int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI);
assert(CCUse >= 0 && "BRC/BCR must use CC");
- Branch->RemoveOperand(CCUse);
+ Branch->removeOperand(CCUse);
// Remove regmask (sibcall).
if (Type == SystemZII::CompareAndSibcall)
- Branch->RemoveOperand(3);
+ Branch->removeOperand(3);
// Remove target (branch or sibcall).
if (Type == SystemZII::CompareAndBranch ||
Type == SystemZII::CompareAndSibcall)
- Branch->RemoveOperand(2);
- Branch->RemoveOperand(1);
- Branch->RemoveOperand(0);
+ Branch->removeOperand(2);
+ Branch->removeOperand(1);
+ Branch->removeOperand(0);
// Rebuild Branch as a fused compare and branch.
// SrcNOps is the number of MI operands of the compare instruction
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 81fca56546f06..3bb13e4c66e52 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -748,8 +748,8 @@ bool SystemZInstrInfo::PredicateInstruction(
if (Opcode == SystemZ::CallJG) {
MachineOperand FirstOp = MI.getOperand(0);
const uint32_t *RegMask = MI.getOperand(1).getRegMask();
- MI.RemoveOperand(1);
- MI.RemoveOperand(0);
+ MI.removeOperand(1);
+ MI.removeOperand(0);
MI.setDesc(get(SystemZ::CallBRCL));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
.addImm(CCValid)
@@ -762,8 +762,8 @@ bool SystemZInstrInfo::PredicateInstruction(
if (Opcode == SystemZ::CallBR) {
MachineOperand Target = MI.getOperand(0);
const uint32_t *RegMask = MI.getOperand(1).getRegMask();
- MI.RemoveOperand(1);
- MI.RemoveOperand(0);
+ MI.removeOperand(1);
+ MI.removeOperand(0);
MI.setDesc(get(SystemZ::CallBCR));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
.addImm(CCValid).addImm(CCMask)
diff --git a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
index 92930dad80ef8..30b22fa1ce92d 100644
--- a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
@@ -162,10 +162,10 @@ bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) {
MachineOperand Src(MI.getOperand(1));
MachineOperand Suppress(MI.getOperand(2));
MachineOperand Mode(MI.getOperand(3));
- MI.RemoveOperand(3);
- MI.RemoveOperand(2);
- MI.RemoveOperand(1);
- MI.RemoveOperand(0);
+ MI.removeOperand(3);
+ MI.removeOperand(2);
+ MI.removeOperand(1);
+ MI.removeOperand(0);
MI.setDesc(TII->get(Opcode));
MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
.add(Dest)
@@ -190,9 +190,9 @@ bool SystemZShortenInst::shortenFusedFPOp(MachineInstr &MI, unsigned Opcode) {
MachineOperand Lhs(LHSMO);
MachineOperand Rhs(RHSMO);
MachineOperand Src(AccMO);
- MI.RemoveOperand(3);
- MI.RemoveOperand(2);
- MI.RemoveOperand(1);
+ MI.removeOperand(3);
+ MI.removeOperand(2);
+ MI.removeOperand(1);
MI.setDesc(TII->get(Opcode));
MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
.add(Src)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
index 17e867e4c7d86..02e873a0f9a6f 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
@@ -1716,7 +1716,7 @@ void WebAssemblyCFGStackify::rewriteDepthImmediates(MachineFunction &MF) {
// Rewrite MBB operands to be depth immediates.
SmallVector<MachineOperand, 4> Ops(MI.operands());
while (MI.getNumOperands() > 0)
- MI.RemoveOperand(MI.getNumOperands() - 1);
+ MI.removeOperand(MI.getNumOperands() - 1);
for (auto MO : Ops) {
if (MO.isMBB()) {
if (MI.getOpcode() == WebAssembly::DELEGATE)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFixBrTableDefaults.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFixBrTableDefaults.cpp
index 5bdec89f1125f..fa5b4a508fa57 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyFixBrTableDefaults.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyFixBrTableDefaults.cpp
@@ -130,7 +130,7 @@ MachineBasicBlock *fixBrTableDefault(MachineInstr &MI, MachineBasicBlock *MBB,
return nullptr;
// Remove the dummy default target and install the real one.
- MI.RemoveOperand(MI.getNumExplicitOperands() - 1);
+ MI.removeOperand(MI.getNumExplicitOperands() - 1);
MI.addOperand(MF, MachineOperand::CreateMBB(TBB));
}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index b110a69202b17..151c2df90d51a 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -579,7 +579,7 @@ LowerCallResults(MachineInstr &CallResults, DebugLoc DL, MachineBasicBlock *BB,
// Move the function pointer to the end of the arguments for indirect calls
if (IsIndirect) {
auto FnPtr = CallParams.getOperand(0);
- CallParams.RemoveOperand(0);
+ CallParams.removeOperand(0);
// For funcrefs, call_indirect is done through __funcref_call_table and the
// funcref is always installed in slot 0 of the table, therefore instead of having
diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
index 3f037e1720c5b..d98c2a4112422 100644
--- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp
+++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
@@ -553,7 +553,7 @@ bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
case X86::PTILELOADDV:
case X86::PTILELOADDT1V: {
for (unsigned i = 2; i > 0; --i)
- MI.RemoveOperand(i);
+ MI.removeOperand(i);
unsigned Opc =
Opcode == X86::PTILELOADDV ? X86::TILELOADD : X86::TILELOADDT1;
MI.setDesc(TII->get(Opc));
@@ -566,7 +566,7 @@ bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
case X86::PTDPBF16PSV: {
MI.untieRegOperand(4);
for (unsigned i = 3; i > 0; --i)
- MI.RemoveOperand(i);
+ MI.removeOperand(i);
unsigned Opc;
switch (Opcode) {
case X86::PTDPBSSDV: Opc = X86::TDPBSSD; break;
@@ -582,13 +582,13 @@ bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
}
case X86::PTILESTOREDV: {
for (int i = 1; i >= 0; --i)
- MI.RemoveOperand(i);
+ MI.removeOperand(i);
MI.setDesc(TII->get(X86::TILESTORED));
return true;
}
case X86::PTILEZEROV: {
for (int i = 2; i > 0; --i) // Remove row, col
- MI.RemoveOperand(i);
+ MI.removeOperand(i);
MI.setDesc(TII->get(X86::TILEZERO));
return true;
}
diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp
index 2f0ab4ca9de4f..34cf2b1c5f6d6 100644
--- a/llvm/lib/Target/X86/X86FloatingPoint.cpp
+++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp
@@ -866,7 +866,7 @@ void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
if (Opcode != -1) {
I->setDesc(TII->get(Opcode));
if (Opcode == X86::FCOMPP || Opcode == X86::UCOM_FPPr)
- I->RemoveOperand(0);
+ I->removeOperand(0);
MI.dropDebugNumber();
} else { // Insert an explicit pop
// If this instruction sets FPSW, which is read in following instruction,
@@ -1034,7 +1034,7 @@ void FPS::handleCall(MachineBasicBlock::iterator &I) {
STReturns |= 1 << getFPReg(Op);
// Remove the operand so that later passes don't see it.
- MI.RemoveOperand(i);
+ MI.removeOperand(i);
--i;
--e;
}
@@ -1098,7 +1098,7 @@ void FPS::handleReturn(MachineBasicBlock::iterator &I) {
LiveMask |= (1 << getFPReg(Op));
// Remove the operand so that later passes don't see it.
- MI.RemoveOperand(i);
+ MI.removeOperand(i);
--i;
--e;
}
@@ -1162,7 +1162,7 @@ void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
unsigned DestReg = getFPReg(MI.getOperand(0));
// Change from the pseudo instruction to the concrete instruction.
- MI.RemoveOperand(0); // Remove the explicit ST(0) operand
+ MI.removeOperand(0); // Remove the explicit ST(0) operand
MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
MI.addOperand(
MachineOperand::CreateReg(X86::ST0, /*isDef*/ true, /*isImp*/ true));
@@ -1210,7 +1210,7 @@ void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
}
// Convert from the pseudo instruction to the concrete instruction.
- MI.RemoveOperand(NumOps - 1); // Remove explicit ST(0) operand
+ MI.removeOperand(NumOps - 1); // Remove explicit ST(0) operand
MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
MI.addOperand(
MachineOperand::CreateReg(X86::ST0, /*isDef*/ false, /*isImp*/ true));
@@ -1263,8 +1263,8 @@ void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
}
// Change from the pseudo instruction to the concrete instruction.
- MI.RemoveOperand(1); // Drop the source operand.
- MI.RemoveOperand(0); // Drop the destination operand.
+ MI.removeOperand(1); // Drop the source operand.
+ MI.removeOperand(0); // Drop the destination operand.
MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
MI.dropDebugNumber();
}
@@ -1464,7 +1464,7 @@ void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
// Change from the pseudo instruction to the concrete instruction.
MI.getOperand(0).setReg(getSTReg(Op1));
- MI.RemoveOperand(1);
+ MI.removeOperand(1);
MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
MI.dropDebugNumber();
@@ -1489,8 +1489,8 @@ void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
// Change the second operand to the stack register that the operand is in.
// Change from the pseudo instruction to the concrete instruction.
- MI.RemoveOperand(0);
- MI.RemoveOperand(1);
+ MI.removeOperand(0);
+ MI.removeOperand(1);
MI.getOperand(0).setReg(getSTReg(Op1));
MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
MI.dropDebugNumber();
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 2b3e0b122bf66..cc0c4770135cd 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -2140,7 +2140,7 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
auto &WorkingMI = cloneIfNew(MI);
WorkingMI.setDesc(get(Opc));
- WorkingMI.RemoveOperand(3);
+ WorkingMI.removeOperand(3);
return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
/*NewMI=*/false,
OpIdx1, OpIdx2);
@@ -2237,7 +2237,7 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
auto &WorkingMI = cloneIfNew(MI);
WorkingMI.setDesc(get(X86::MOVSDrr));
- WorkingMI.RemoveOperand(3);
+ WorkingMI.removeOperand(3);
return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
OpIdx1, OpIdx2);
}
@@ -4374,7 +4374,7 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
}
CmpInstr.setDesc(get(NewOpcode));
- CmpInstr.RemoveOperand(0);
+ CmpInstr.removeOperand(0);
// Mutating this instruction invalidates any debug data associated with it.
CmpInstr.dropDebugNumber();
// Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
@@ -4810,7 +4810,7 @@ static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
MIB->setDesc(TII.get(X86::POP32r));
}
- MIB->RemoveOperand(1);
+ MIB->removeOperand(1);
MIB->addImplicitDefUseOperands(*MBB.getParent());
// Build CFI if necessary.
@@ -4917,7 +4917,7 @@ static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
MIB->setDesc(Desc);
int64_t ShiftAmt = MIB->getOperand(2).getImm();
// Temporarily remove the immediate so we can add another source register.
- MIB->RemoveOperand(2);
+ MIB->removeOperand(2);
// Add the register. Don't copy the kill flag if there is one.
MIB.addReg(MIB.getReg(1),
getUndefRegState(MIB->getOperand(1).isUndef()));
@@ -5025,7 +5025,7 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
unsigned MaskState = getRegState(MIB->getOperand(1));
unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
- MI.RemoveOperand(1);
+ MI.removeOperand(1);
MIB->setDesc(get(Opc));
// VPTERNLOG needs 3 register inputs and an immediate.
// 0xff will return 1s for any input.
diff --git a/llvm/lib/Target/X86/X86InstructionSelector.cpp b/llvm/lib/Target/X86/X86InstructionSelector.cpp
index a46dfd4f27c98..f4abb3a83c316 100644
--- a/llvm/lib/Target/X86/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/X86InstructionSelector.cpp
@@ -537,12 +537,12 @@ bool X86InstructionSelector::selectLoadStoreOp(MachineInstr &I,
I.setDesc(TII.get(NewOpc));
MachineInstrBuilder MIB(MF, I);
if (Opc == TargetOpcode::G_LOAD) {
- I.RemoveOperand(1);
+ I.removeOperand(1);
addFullAddress(MIB, AM);
} else {
// G_STORE (VAL, Addr), X86Store instruction (Addr, VAL)
- I.RemoveOperand(1);
- I.RemoveOperand(0);
+ I.removeOperand(1);
+ I.removeOperand(0);
addFullAddress(MIB, AM).addUse(DefReg);
}
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
@@ -625,7 +625,7 @@ bool X86InstructionSelector::selectGlobalValue(MachineInstr &I,
I.setDesc(TII.get(NewOpc));
MachineInstrBuilder MIB(MF, I);
- I.RemoveOperand(1);
+ I.removeOperand(1);
addFullAddress(MIB, AM);
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
diff --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
index dba11e8b40001..882dae7e1adea 100644
--- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
+++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
@@ -356,8 +356,8 @@ static void canonicalizePHIOperands(MachineFunction &MF) {
int OpIdx = DupIndices.pop_back_val();
// Remove both the block and value operand, again in reverse order to
// preserve indices.
- MI.RemoveOperand(OpIdx + 1);
- MI.RemoveOperand(OpIdx);
+ MI.removeOperand(OpIdx + 1);
+ MI.removeOperand(OpIdx);
}
Preds.clear();
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