[PATCH] D121571: [TableGen] X86 mnemonic tables backend

[Kan Shengchen via Phabricator via llvm-commits]

skan added inline comments.


================
Comment at: llvm/utils/TableGen/X86MnemonicTables.cpp:44
+    Record *Def = I->TheDef;
+    if (!Def->isSubClassOf("X86Inst") || // Filter non-X86 instructions
+        // Skip pseudo instructions as they may contain non-alnum characters in
----------------
Need to check the `Form` is not neither `Pseudo` or  `PrefixByte`.


================
Comment at: llvm/utils/TableGen/X86MnemonicTables.cpp:47
+        // mnemonic
+        Def->getValueAsBit("isCodeGenOnly") ||
+        // Non-parsable instruction defs contain prefix as part of AsmString
----------------
Need to check `ForceDisassemble` is not true for isCodeGenOnly


================
Comment at: llvm/utils/TableGen/X86MnemonicTables.cpp:73
+    OS << "bool is" << Mnemonic.upper() << "(unsigned Opcode) {\n"
+       << "\tswitch (Opcode) {\n";
+    for (const CodeGenInstruction *CGI : MnemonicToCGInstrMap[Mnemonic]) {
----------------
Avoid using `switch` clause when there is only one instruction.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121571/new/

https://reviews.llvm.org/D121571