[PATCH] D120958: [TableGen] Add support for variable length instruction in decoder generator
Sheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 15 18:52:23 PDT 2022
0x59616e added a comment.
In D120958#3383624 <https://reviews.llvm.org/D120958#3383624>, @myhsu wrote:
> In D120958#3382237 <https://reviews.llvm.org/D120958#3382237>, @0x59616e wrote:
>
>> We can traverse the Segments of VarLenInst and use `CGIOperandList::OperandInfo::ParseOperandName` to get the operand number, and then add that Segments into the correspoding `OpInfo` according to the operand number.
>>
>> For example, if we find "dst.reg" and use `CGIOperandList::OperandInfo::ParseOperandName` and know "Oh, this is the third operand", then we can add this into the third `OpInfo`.
>>
>> In this way we can avoid overload `BitsInit` completely.
>
> This approach sounds reasonable to me
Great ! I'll materialize it this weekend.
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https://reviews.llvm.org/D120958/new/
https://reviews.llvm.org/D120958
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