[llvm] 5464fd3 - [AMDGPU] Fix typo consecutive in GCNNSAReassign

[Joe Nash via llvm-commits]

Author: Joe Nash
Date: 2022-03-15T12:42:52-04:00
New Revision: 5464fd36bad57e703d276022bd27b858689b4f61

URL: https://github.com/llvm/llvm-project/commit/5464fd36bad57e703d276022bd27b858689b4f61
DIFF: https://github.com/llvm/llvm-project/commit/5464fd36bad57e703d276022bd27b858689b4f61.diff

LOG: [AMDGPU] Fix typo consecutive in GCNNSAReassign

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
index c39e47363d76f..68e72bc00874c 100644
--- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
@@ -184,7 +184,7 @@ GCNNSAReassign::CheckNSA(const MachineInstr &MI, bool Fast) const {
       // logic to find free registers will be much more complicated with much
       // less chances for success. That seems reasonable to assume that in most
       // cases a tuple is used because a vector variable contains 
diff erent
-      // parts of an address and it is either already consequitive or cannot
+      // parts of an address and it is either already consecutive or cannot
       // be reassigned if not. If needed it is better to rely on register
       // coalescer to process such address tuples.
       if (MRI->getRegClass(Reg) != &AMDGPU::VGPR_32RegClass || Op.getSubReg())