[llvm] 06c5d74 - [RISCV] Remove lowerSPLAT_VECTOR
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 15 08:22:41 PDT 2022
Author: Craig Topper
Date: 2022-03-15T08:22:13-07:00
New Revision: 06c5d74090ff00346b8c286bcc27fffbc529cd45
URL: https://github.com/llvm/llvm-project/commit/06c5d74090ff00346b8c286bcc27fffbc529cd45
DIFF: https://github.com/llvm/llvm-project/commit/06c5d74090ff00346b8c286bcc27fffbc529cd45.diff
LOG: [RISCV] Remove lowerSPLAT_VECTOR
This code handles fixed vector SPLAT_VECTOR, but is never called in
any tests.
We only form fixed vector splat vectors for vXi64 on RV32 as part
of DAGCombine. This will be type legalized to SPLAT_VECTOR_PARTS.
So the Custom handling for SPLAT_VECTOR is never needed.
This patch makes SPLAT_VECTOR for vXi64 'Legal' on RV32 so that
DAGCombine will create it, but there's no need for Custom handler.
It will still be type legalized to SPLAT_VECTOR_PARTS.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D121673
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 43fc52d17149a..38feb31c2101d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -849,12 +849,13 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
continue;
}
- // Use SPLAT_VECTOR to prevent type legalization from destroying the
- // splats when type legalizing i64 scalar on RV32.
+ // Make SPLAT_VECTOR Legal so DAGCombine will convert splat vectors to
+ // it before type legalization for i64 vectors on RV32. It will then be
+ // type legalized to SPLAT_VECTOR_PARTS which we need to Custom handle.
// FIXME: Use SPLAT_VECTOR for all types? DAGCombine probably needs
// improvements first.
if (!Subtarget.is64Bit() && VT.getVectorElementType() == MVT::i64) {
- setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
+ setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
setOperationAction(ISD::SPLAT_VECTOR_PARTS, VT, Custom);
}
@@ -1885,24 +1886,6 @@ static SDValue lowerFROUND(SDValue Op, SelectionDAG &DAG) {
return DAG.getSelect(DL, VT, Setcc, Truncated, Src);
}
-static SDValue lowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG,
- const RISCVSubtarget &Subtarget) {
- MVT VT = Op.getSimpleValueType();
- assert(VT.isFixedLengthVector() && "Unexpected vector!");
-
- MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
-
- SDLoc DL(Op);
- SDValue Mask, VL;
- std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
-
- unsigned Opc =
- VT.isFloatingPoint() ? RISCVISD::VFMV_V_F_VL : RISCVISD::VMV_V_X_VL;
- SDValue Splat = DAG.getNode(Opc, DL, ContainerVT, DAG.getUNDEF(ContainerVT),
- Op.getOperand(0), VL);
- return convertFromScalableVector(VT, Splat, DAG, Subtarget);
-}
-
struct VIDSequence {
int64_t StepNumerator;
unsigned StepDenominator;
@@ -3537,7 +3520,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::SPLAT_VECTOR:
if (Op.getValueType().getVectorElementType() == MVT::i1)
return lowerVectorMaskSplat(Op, DAG);
- return lowerSPLAT_VECTOR(Op, DAG, Subtarget);
+ return SDValue();
case ISD::VECTOR_SHUFFLE:
return lowerVECTOR_SHUFFLE(Op, DAG, Subtarget);
case ISD::CONCAT_VECTORS: {
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