[llvm] 72a9e5f - [AMDGPU] Restrict machine copy propagation from creating unaligned classes
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 14 14:09:58 PDT 2022
Author: Stanislav Mekhanoshin
Date: 2022-03-14T14:09:40-07:00
New Revision: 72a9e5f8919ec8b16a91e01989f1db028650628e
URL: https://github.com/llvm/llvm-project/commit/72a9e5f8919ec8b16a91e01989f1db028650628e
DIFF: https://github.com/llvm/llvm-project/commit/72a9e5f8919ec8b16a91e01989f1db028650628e.diff
LOG: [AMDGPU] Restrict machine copy propagation from creating unaligned classes
Fixes: SWDEV-326366
Differential Revision: https://reviews.llvm.org/D121491
Added:
llvm/test/CodeGen/AMDGPU/mcp-aligned-vgprs.mir
Modified:
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 6fcd2d90cca9f..7f7ea8ace10b3 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4740,26 +4740,37 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {
"Unexpected scalar opcode without corresponding vector one!");
}
-static unsigned adjustAllocatableRegClass(const GCNSubtarget &ST,
- const MachineRegisterInfo &MRI,
- const MCInstrDesc &TID,
- unsigned RCID,
- bool IsAllocatable) {
+static const TargetRegisterClass *
+adjustAllocatableRegClass(const GCNSubtarget &ST, const SIRegisterInfo &RI,
+ const MachineRegisterInfo &MRI,
+ const MCInstrDesc &TID, unsigned RCID,
+ bool IsAllocatable) {
if ((IsAllocatable || !ST.hasGFX90AInsts() || !MRI.reservedRegsFrozen()) &&
(((TID.mayLoad() || TID.mayStore()) &&
!(TID.TSFlags & SIInstrFlags::VGPRSpill)) ||
(TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::MIMG)))) {
switch (RCID) {
- case AMDGPU::AV_32RegClassID: return AMDGPU::VGPR_32RegClassID;
- case AMDGPU::AV_64RegClassID: return AMDGPU::VReg_64RegClassID;
- case AMDGPU::AV_96RegClassID: return AMDGPU::VReg_96RegClassID;
- case AMDGPU::AV_128RegClassID: return AMDGPU::VReg_128RegClassID;
- case AMDGPU::AV_160RegClassID: return AMDGPU::VReg_160RegClassID;
+ case AMDGPU::AV_32RegClassID:
+ RCID = AMDGPU::VGPR_32RegClassID;
+ break;
+ case AMDGPU::AV_64RegClassID:
+ RCID = AMDGPU::VReg_64RegClassID;
+ break;
+ case AMDGPU::AV_96RegClassID:
+ RCID = AMDGPU::VReg_96RegClassID;
+ break;
+ case AMDGPU::AV_128RegClassID:
+ RCID = AMDGPU::VReg_128RegClassID;
+ break;
+ case AMDGPU::AV_160RegClassID:
+ RCID = AMDGPU::VReg_160RegClassID;
+ break;
default:
break;
}
}
- return RCID;
+
+ return RI.getProperlyAlignedRC(RI.getRegClass(RCID));
}
const TargetRegisterClass *SIInstrInfo::getRegClass(const MCInstrDesc &TID,
@@ -4789,9 +4800,8 @@ const TargetRegisterClass *SIInstrInfo::getRegClass(const MCInstrDesc &TID,
AMDGPU::OpName::data1) != -1;
}
}
- RegClass = adjustAllocatableRegClass(ST, MF.getRegInfo(), TID, RegClass,
- IsAllocatable);
- return RI.getRegClass(RegClass);
+ return adjustAllocatableRegClass(ST, RI, MF.getRegInfo(), TID, RegClass,
+ IsAllocatable);
}
const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
@@ -4808,8 +4818,7 @@ const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
}
unsigned RCID = Desc.OpInfo[OpNo].RegClass;
- RCID = adjustAllocatableRegClass(ST, MRI, Desc, RCID, true);
- return RI.getRegClass(RCID);
+ return adjustAllocatableRegClass(ST, RI, MRI, Desc, RCID, true);
}
void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index d2622d116d5c1..120b601f9a042 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3014,6 +3014,25 @@ bool SIRegisterInfo::isProperlyAlignedRC(const TargetRegisterClass &RC) const {
return true;
}
+const TargetRegisterClass *
+SIRegisterInfo::getProperlyAlignedRC(const TargetRegisterClass *RC) const {
+ if (!RC || !ST.needsAlignedVGPRs())
+ return RC;
+
+ unsigned Size = getRegSizeInBits(*RC);
+ if (Size <= 32)
+ return RC;
+
+ if (isVGPRClass(RC))
+ return getAlignedVGPRClassForBitWidth(Size);
+ if (isAGPRClass(RC))
+ return getAlignedAGPRClassForBitWidth(Size);
+ if (isVectorSuperClass(RC))
+ return getAlignedVectorSuperClassForBitWidth(Size);
+
+ return RC;
+}
+
bool SIRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
switch (PhysReg) {
case AMDGPU::SGPR_NULL:
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 1035fb735d37f..93b1c65e2ebec 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -379,6 +379,11 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// the subtarget.
bool isProperlyAlignedRC(const TargetRegisterClass &RC) const;
+ // Given \p RC returns corresponding aligned register class if required
+ // by the subtarget.
+ const TargetRegisterClass *
+ getProperlyAlignedRC(const TargetRegisterClass *RC) const;
+
/// Return all SGPR128 which satisfy the waves per execution unit requirement
/// of the subtarget.
ArrayRef<MCPhysReg> getAllSGPR128(const MachineFunction &MF) const;
diff --git a/llvm/test/CodeGen/AMDGPU/mcp-aligned-vgprs.mir b/llvm/test/CodeGen/AMDGPU/mcp-aligned-vgprs.mir
new file mode 100644
index 0000000000000..bb2126d6fecb9
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/mcp-aligned-vgprs.mir
@@ -0,0 +1,28 @@
+# RUN: llc -march=amdgcn -mcpu=gfx90a -run-pass=machine-cp -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
+
+# GCN-LABEL: name: mcp_aligned_vgprs
+# GCN: $vgpr0_vgpr1 = V_PK_MUL_F32 0, $sgpr0_sgpr1
+# GCN: $vgpr3_vgpr4 = COPY killed renamable $vgpr0_vgpr1
+---
+name: mcp_aligned_vgprs
+body: |
+ bb.0.entry:
+
+ renamable $vgpr0_vgpr1 = V_PK_MUL_F32 0, $sgpr0_sgpr1, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ renamable $vgpr3_vgpr4 = COPY killed renamable $vgpr0_vgpr1
+ S_ENDPGM 0, implicit $vgpr3_vgpr4
+...
+
+# GCN-LABEL: name: mcp_aligned_agprs
+# GCN: $agpr0_agpr1 = GLOBAL_LOAD_DWORDX2_SADDR $sgpr0_sgpr1, $vgpr10
+# GCN: $agpr3_agpr4 = COPY killed renamable $agpr0_agpr1
+---
+name: mcp_aligned_agprs
+body: |
+ bb.0.entry:
+
+ renamable $agpr0_agpr1 = GLOBAL_LOAD_DWORDX2_SADDR $sgpr0_sgpr1, $vgpr10, 0, 0, implicit $exec
+ renamable $agpr3_agpr4 = COPY killed renamable $agpr0_agpr1
+ S_ENDPGM 0, implicit $agpr3_agpr4
+
+...
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