[PATCH] D121571: [TableGen][X86] X86 mnemonic tables backend

[Amir Ayupov via Phabricator via llvm-commits]

Amir added a comment.

In D121571#3378638 <https://reviews.llvm.org/D121571#3378638>, @craig.topper wrote:

> I was looking at the code in `replaceRegWithReg` where isAND, isCMP, etc. are used. I don't understand this loop.
>
>   for (unsigned Index = InstDesc.getNumDefs() + (HasLHS ? 1 : 0),
>                 E = InstDesc.getNumOperands();
>        Index != E; ++Index) {
>
> HasLHS is set for all AND, ADD, SUB instructions, but some of them are RMW memory operations where getNumDefs() == 0. And there are 5 source address operands. The HasLHS will be 1 and skip the first of those 5 operands. Is that correct?

Thanks for flagging, it doesn't seem right. The code may have borrowed from a different function (replaceMemOperandWithImm) where the only opcode group having RMW semantics was TESTmr and it was handled separately. For the purposes of replaceRegWithReg, HasLHS logic is not applicable to RMW instructions. I'll address that separately.


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