[PATCH] D121449: [AArch64] Combine ISD::SETCC into AArch64ISD::ANDS

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Thanks for the investigation.  I think the options are:

1. DAG combine for setcc (srl x, imm), 0, ne ==> setcc (and x, (-1 << imm)), 0, ne
2. update emitComparison to replace replace single use srl with ands.

I don't see "performSUBSCombine: subs (srl x, imm), 0 ==> ands x, (-1 << imm)" as an option as the only reason we would see this idiom is when emitComparison emits it.

Of the two approaches (1) is my favourite purely because it tries to canonicalise the DAG, which is always beneficial.  I say this because I guess if we're seeing `srl` as something to support then how far away are we from wanting to support `shl` and thus I'd rather canonicalise the DAG rather than make emitComparison progressively more complex.


Repository:
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  https://reviews.llvm.org/D121449/new/

https://reviews.llvm.org/D121449