[PATCH] D121180: [AArch64] Perform last active true vector combine

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added inline comments.
This revision is now accepted and ready to land.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14441
+  unsigned NumEls = OpVT.getVectorElementCount().getKnownMinValue();
+  if (VS.getConstantOperandVal(0) != NumEls)
+    return SDValue();
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Given it's an equality test it probably doesn't matter but `ISD::VSCALE`'s multiplier is signed whereas `getConstantOperandVal` returns `uint64_t`.


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  https://reviews.llvm.org/D121180/new/

https://reviews.llvm.org/D121180