[PATCH] D121180: [AArch64] Perform last active true vector combine
Paul Walker via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 14 08:45:54 PDT 2022
paulwalker-arm accepted this revision.
paulwalker-arm added inline comments.
This revision is now accepted and ready to land.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14441
+ unsigned NumEls = OpVT.getVectorElementCount().getKnownMinValue();
+ if (VS.getConstantOperandVal(0) != NumEls)
+ return SDValue();
----------------
Given it's an equality test it probably doesn't matter but `ISD::VSCALE`'s multiplier is signed whereas `getConstantOperandVal` returns `uint64_t`.
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https://reviews.llvm.org/D121180/new/
https://reviews.llvm.org/D121180
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