[PATCH] D121397: [AMDGPU] Correct gfx940 memory model documentation.

[Tony Tye via Phabricator via llvm-commits]

t-tye added inline comments.


================
Comment at: llvm/docs/AMDGPUUsage.rst:8721
 
+  * Atomic operations re-using sc0 bit to indicate an old value shall be
+    returned with only sc1 being used for coherency requests.
----------------
How about:

Atomic read-modify-write instructions implicitly bypass the L1 cache. Therefore, they do not use the sc0 bit for coherence and instead use it to indicate if the instruction returns the original value being updated. They do use sc1 to indicate system or agent scope coherence.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121397/new/

https://reviews.llvm.org/D121397