[PATCH] D121598: [RISCV] Select SRLI+SLLI for AND with leading ones mask

[Haocong Lu via Phabricator via llvm-commits]

Luhaocong created this revision.
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Select SRLI+SLLI for AND if its second operand is a leading ones mask.
It's useful in RV64 when the mask cannot be generated by LUI.


https://reviews.llvm.org/D121598

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/and.ll
  llvm/test/CodeGen/RISCV/copysign-casts.ll
  llvm/test/CodeGen/RISCV/double-arith.ll
  llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/double-intrinsics.ll
  llvm/test/CodeGen/RISCV/float-arith.ll
  llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/float-intrinsics.ll
  llvm/test/CodeGen/RISCV/half-arith.ll
  llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/half-intrinsics.ll
  llvm/test/CodeGen/RISCV/rem.ll
  llvm/test/CodeGen/RISCV/rv32zbp.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll
  llvm/test/CodeGen/RISCV/shift-and.ll
  llvm/test/CodeGen/RISCV/srem-lkk.ll

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