[PATCH] D121449: [AArch64] Combine ISD::SETCC into AArch64ISD::ANDS

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

An alternative suggested is to perhaps keep the DAGCombine but have it just canonicalise the shift pattern to use `ISD::AND` [1], that way I believe the existing code in `emitComparison` will do what you need.  If that works then that's my preferred option as it keeps things simple and relatively target agnostic.

[1]
`setcc (srl x, imm), 0, ne ==> setcc (tst x, (-1 << imm)), 0, ne`


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  https://reviews.llvm.org/D121449/new/

https://reviews.llvm.org/D121449