[PATCH] D121076: [MLIR][Python] Add SCFIfOp Python binding

Mon Mar 7 09:18:48 PST 2022

chhzh123 updated this revision to Diff 413518.
chhzh123 added a comment.
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Fix signature and add tests

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121076/new/

https://reviews.llvm.org/D121076

Files:
  README.md
  clang-tools-extra/docs/clang-tidy/Contributing.rst
  clang/docs/ClangFormattedStatus.rst
  clang/docs/DataFlowAnalysisIntro.md
  clang/docs/analyzer/checkers.rst
  clang/docs/tools/clang-formatted-files.txt
  clang/include/clang/Basic/Module.h
  clang/include/clang/Parse/Parser.h
  clang/include/clang/Sema/DeclSpec.h
  clang/include/clang/Tooling/Syntax/Pseudo/DirectiveMap.h
  clang/include/clang/Tooling/Syntax/Pseudo/Preprocess.h
  clang/lib/Basic/Module.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Format/UnwrappedLineFormatter.cpp
  clang/lib/Parse/ParseDecl.cpp
  clang/lib/Parse/ParseDeclCXX.cpp
  clang/lib/Parse/ParseExprCXX.cpp
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Parse/ParseStmt.cpp
  clang/lib/Parse/ParseTentative.cpp
  clang/lib/Serialization/ASTWriter.cpp
  clang/lib/StaticAnalyzer/Checkers/DeadStoresChecker.cpp
  clang/lib/StaticAnalyzer/Checkers/GenericTaintChecker.cpp
  clang/lib/Tooling/Syntax/Pseudo/CMakeLists.txt
  clang/lib/Tooling/Syntax/Pseudo/DirectiveMap.cpp
  clang/lib/Tooling/Syntax/Pseudo/Preprocess.cpp
  clang/lib/Tooling/Syntax/Pseudo/README.md
  clang/test/Analysis/taint-generic.c
  clang/test/CodeGen/PowerPC/builtins-ppc-fma.c
  clang/test/CodeGen/PowerPC/builtins-ppc-fpconstrained.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
  clang/test/Modules/Inputs/AddRemoveIrrelevantModuleMap/a.modulemap
  clang/test/Modules/Inputs/AddRemoveIrrelevantModuleMap/b.modulemap
  clang/test/Modules/add-remove-irrelevant-module-map.m
  clang/test/OpenMP/irbuilder_nested_openmp_parallel_empty.c
  clang/test/OpenMP/irbuilder_nested_parallel_for.c
  clang/test/Syntax/lex.c
  clang/tools/clang-pseudo/ClangPseudo.cpp
  clang/unittests/Format/FormatTest.cpp
  clang/unittests/Tooling/LookupTest.cpp
  clang/unittests/Tooling/Syntax/Pseudo/CMakeLists.txt
  clang/unittests/Tooling/Syntax/Pseudo/DirectiveMapTest.cpp
  clang/unittests/Tooling/Syntax/Pseudo/PreprocessTest.cpp
  flang/tools/bbc/bbc.cpp
  flang/tools/fir-opt/fir-opt.cpp
  flang/tools/tco/tco.cpp
  libc/loader/linux/x86_64/start.cpp
  libcxx/docs/ReleaseNotes.rst
  libcxx/include/CMakeLists.txt
  libcxx/include/__algorithm/ranges_max_element.h
  libcxx/include/__memory/unique_ptr.h
  libcxx/include/__ranges/access.h
  libcxx/include/algorithm
  libcxx/include/cuchar
  libcxx/include/module.modulemap
  libcxx/include/uchar.h
  libcxx/test/libcxx/clang_tidy.sh.cpp
  libcxx/test/libcxx/diagnostics/detail.headers/algorithm/ranges_max_element.module.verify.cpp
  libcxx/test/libcxx/double_include.sh.cpp
  libcxx/test/libcxx/min_max_macros.compile.pass.cpp
  libcxx/test/libcxx/nasty_macros.compile.pass.cpp
  libcxx/test/libcxx/no_assert_include.compile.pass.cpp
  libcxx/test/libcxx/strings/c.strings/version_cuchar.pass.cpp
  libcxx/test/std/algorithms/alg.sorting/alg.min.max/ranges.max_element.pass.cpp
  libcxx/test/std/depr/depr.c.headers/uchar_h.compile.pass.cpp
  libcxx/test/std/depr/depr.c.headers/uchar_h.pass.cpp
  libcxx/test/std/library/description/conventions/customization.point.object/niebloid.compile.pass.cpp
  libcxx/test/std/ranges/range.access/begin.sizezero.pass.cpp
  libcxx/test/std/ranges/range.access/end.sizezero.pass.cpp
  libcxx/test/std/strings/c.strings/cuchar.compile.pass.cpp
  libcxx/test/std/strings/c.strings/cuchar.pass.cpp
  libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.create/make_unique.sizezero.pass.cpp
  libcxx/utils/generate_header_inclusion_tests.py
  llvm/CODE_OWNERS.TXT
  llvm/CREDITS.TXT
  llvm/include/llvm/Analysis/ConstraintSystem.h
  llvm/include/llvm/Analysis/ScalarEvolution.h
  llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/include/llvm/IR/VectorBuilder.h
  llvm/include/llvm/ObjCopy/MachO/MachOConfig.h
  llvm/include/llvm/Transforms/IPO/Attributor.h
  llvm/include/llvm/Transforms/Utils/CodeExtractor.h
  llvm/include/llvm/module.modulemap
  llvm/lib/Analysis/ScalarEvolution.cpp
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/DebugInfo/PDB/Native/PDBStringTableBuilder.cpp
  llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
  llvm/lib/IR/CMakeLists.txt
  llvm/lib/IR/Value.cpp
  llvm/lib/IR/VectorBuilder.cpp
  llvm/lib/ObjCopy/MachO/MachOObjcopy.cpp
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AMDGPU/AMDGPU.td
  llvm/lib/Target/AMDGPU/GCNSubtarget.h
  llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  llvm/lib/Target/Hexagon/HexagonArch.h
  llvm/lib/Target/Hexagon/HexagonDepArch.h
  llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
  llvm/lib/Target/Hexagon/HexagonSubtarget.h
  llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/VE/VECustomDAG.cpp
  llvm/lib/Target/VE/VECustomDAG.h
  llvm/lib/Target/VE/VEISelLowering.h
  llvm/lib/Target/VE/VEInstrInfo.cpp
  llvm/lib/Target/VE/VVPISelLowering.cpp
  llvm/lib/Transforms/Coroutines/CoroElide.cpp
  llvm/lib/Transforms/Coroutines/CoroFrame.cpp
  llvm/lib/Transforms/Coroutines/CoroInternal.h
  llvm/lib/Transforms/Coroutines/CoroSplit.cpp
  llvm/lib/Transforms/IPO/Attributor.cpp
  llvm/lib/Transforms/IPO/AttributorAttributes.cpp
  llvm/lib/Transforms/IPO/HotColdSplitting.cpp
  llvm/lib/Transforms/IPO/IROutliner.cpp
  llvm/lib/Transforms/IPO/OpenMPOpt.cpp
  llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
  llvm/lib/Transforms/Scalar/LoopPassManager.cpp
  llvm/lib/Transforms/Scalar/LoopSink.cpp
  llvm/lib/Transforms/Utils/CodeExtractor.cpp
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  llvm/test/Analysis/CostModel/AArch64/arith.ll
  llvm/test/Analysis/CostModel/AArch64/cast.ll
  llvm/test/Analysis/CostModel/AArch64/min-max.ll
  llvm/test/Analysis/CostModel/X86/gather-i16-with-i8-index.ll
  llvm/test/Analysis/CostModel/X86/gather-i32-with-i8-index.ll
  llvm/test/Analysis/CostModel/X86/gather-i64-with-i8-index.ll
  llvm/test/Analysis/CostModel/X86/gather-i8-with-i8-index.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-5.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2-indices-0u.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-01u.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-0uu.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-012u.ll
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  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-5.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-4.ll
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  llvm/test/Analysis/CostModel/X86/masked-gather-i32-with-i8-index.ll
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  llvm/test/Analysis/CostModel/X86/masked-interleaved-load-i16.ll
  llvm/test/Analysis/CostModel/X86/masked-interleaved-store-i16.ll
  llvm/test/Analysis/CostModel/X86/masked-load-i16.ll
  llvm/test/Analysis/CostModel/X86/masked-load-i32.ll
  llvm/test/Analysis/CostModel/X86/masked-load-i64.ll
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  llvm/test/Analysis/CostModel/X86/masked-scatter-i32-with-i8-index.ll
  llvm/test/Analysis/CostModel/X86/masked-scatter-i64-with-i8-index.ll
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  llvm/test/Analysis/CostModel/X86/masked-store-i64.ll
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  llvm/test/Analysis/CostModel/X86/scatter-i16-with-i8-index.ll
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  llvm/test/CodeGen/AArch64/arm64-vshuffle.ll
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  llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
  llvm/test/CodeGen/AArch64/neon-extracttruncate.ll
  llvm/test/CodeGen/AMDGPU/back-off-barrier-subtarget-feature.ll
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  llvm/test/CodeGen/AMDGPU/waitcnt-preexisting-vscnt.mir
  llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
  llvm/test/CodeGen/LoongArch/1ri.mir
  llvm/test/CodeGen/LoongArch/2ri.mir
  llvm/test/CodeGen/LoongArch/3ri.mir
  llvm/test/CodeGen/LoongArch/misc.mir
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
  llvm/test/CodeGen/PowerPC/vec-itofp.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
  llvm/test/CodeGen/Thumb2/mve-vst3.ll
  llvm/test/CodeGen/VE/Packed/vec_load.ll
  llvm/test/CodeGen/VE/Packed/vec_store.ll
  llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
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  llvm/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt
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