[PATCH] D121571: [TableGen][X86] X86 mnemonic tables backend

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I was looking at the code in `replaceRegWithReg` where isAND, isCMP, etc. are used. I don't understand this loop.

  for (unsigned Index = InstDesc.getNumDefs() + (HasLHS ? 1 : 0),
                E = InstDesc.getNumOperands();
       Index != E; ++Index) {

HasLHS is set for all AND, ADD, SUB instructions, but some of them are RMW memory operations where getNumDefs() == 0. And there are 5 source address operands. The HasLHS will be 1 and skip the first of those 5 operands. Is that correct?


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https://reviews.llvm.org/D121571