[PATCH] D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32

[Lehua Ding via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1648852c9807: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32 (authored by lhtin).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120899/new/

https://reviews.llvm.org/D120899

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/rvv/masked-vslide1down-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vslide1down-constant-vl-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslide1up-constant-vl-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll

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