[llvm] b55a77d - [RISCV] Add Zbp command lines to bswap-bitreverse.ll. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 12 17:01:45 PST 2022
Author: Craig Topper
Date: 2022-03-12T16:23:42-08:00
New Revision: b55a77d2229d5e2d355a14a537fd6c98607021de
URL: https://github.com/llvm/llvm-project/commit/b55a77d2229d5e2d355a14a537fd6c98607021de
DIFF: https://github.com/llvm/llvm-project/commit/b55a77d2229d5e2d355a14a537fd6c98607021de.diff
LOG: [RISCV] Add Zbp command lines to bswap-bitreverse.ll. NFC
Added:
Modified:
llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll b/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
index d442602ef5ab1..489e117b6401d 100644
--- a/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
+++ b/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
@@ -11,6 +11,10 @@
; RUN: | FileCheck %s -check-prefixes=RV32ZB,RV32ZBKB
; RUN: llc -mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=RV64ZB,RV64ZBKB
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefixes=RV32ZBP
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefixes=RV64ZBP
declare i16 @llvm.bswap.i16(i16)
declare i32 @llvm.bswap.i32(i32)
@@ -48,6 +52,16 @@ define i16 @test_bswap_i16(i16 %a) nounwind {
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 48
; RV64ZB-NEXT: ret
+;
+; RV32ZBP-LABEL: test_bswap_i16:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev8.h a0, a0
+; RV32ZBP-NEXT: ret
+;
+; RV64ZBP-LABEL: test_bswap_i16:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev8.h a0, a0
+; RV64ZBP-NEXT: ret
%tmp = call i16 @llvm.bswap.i16(i16 %a)
ret i16 %tmp
}
@@ -95,6 +109,16 @@ define i32 @test_bswap_i32(i32 %a) nounwind {
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: srli a0, a0, 32
; RV64ZB-NEXT: ret
+;
+; RV32ZBP-LABEL: test_bswap_i32:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev8 a0, a0
+; RV32ZBP-NEXT: ret
+;
+; RV64ZBP-LABEL: test_bswap_i32:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev8.w a0, a0
+; RV64ZBP-NEXT: ret
%tmp = call i32 @llvm.bswap.i32(i32 %a)
ret i32 %tmp
}
@@ -169,6 +193,18 @@ define i64 @test_bswap_i64(i64 %a) nounwind {
; RV64ZB: # %bb.0:
; RV64ZB-NEXT: rev8 a0, a0
; RV64ZB-NEXT: ret
+;
+; RV32ZBP-LABEL: test_bswap_i64:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev8 a2, a1
+; RV32ZBP-NEXT: rev8 a1, a0
+; RV32ZBP-NEXT: mv a0, a2
+; RV32ZBP-NEXT: ret
+;
+; RV64ZBP-LABEL: test_bswap_i64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev8 a0, a0
+; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.bswap.i64(i64 %a)
ret i64 %tmp
}
@@ -263,6 +299,16 @@ define i8 @test_bitreverse_i8(i8 %a) nounwind {
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 56
; RV64ZBKB-NEXT: ret
+;
+; RV32ZBP-LABEL: test_bitreverse_i8:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev.b a0, a0
+; RV32ZBP-NEXT: ret
+;
+; RV64ZBP-LABEL: test_bitreverse_i8:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev.b a0, a0
+; RV64ZBP-NEXT: ret
%tmp = call i8 @llvm.bitreverse.i8(i8 %a)
ret i8 %tmp
}
@@ -391,6 +437,16 @@ define i16 @test_bitreverse_i16(i16 %a) nounwind {
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 48
; RV64ZBKB-NEXT: ret
+;
+; RV32ZBP-LABEL: test_bitreverse_i16:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev.h a0, a0
+; RV32ZBP-NEXT: ret
+;
+; RV64ZBP-LABEL: test_bitreverse_i16:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev.h a0, a0
+; RV64ZBP-NEXT: ret
%tmp = call i16 @llvm.bitreverse.i16(i16 %a)
ret i16 %tmp
}
@@ -537,6 +593,16 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind {
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 32
; RV64ZBKB-NEXT: ret
+;
+; RV32ZBP-LABEL: test_bitreverse_i32:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev a0, a0
+; RV32ZBP-NEXT: ret
+;
+; RV64ZBP-LABEL: test_bitreverse_i32:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev.w a0, a0
+; RV64ZBP-NEXT: ret
%tmp = call i32 @llvm.bitreverse.i32(i32 %a)
ret i32 %tmp
}
@@ -740,6 +806,18 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind {
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: ret
+;
+; RV32ZBP-LABEL: test_bitreverse_i64:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev a2, a1
+; RV32ZBP-NEXT: rev a1, a0
+; RV32ZBP-NEXT: mv a0, a2
+; RV32ZBP-NEXT: ret
+;
+; RV64ZBP-LABEL: test_bitreverse_i64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev a0, a0
+; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.bitreverse.i64(i64 %a)
ret i64 %tmp
}
@@ -863,6 +941,16 @@ define i16 @test_bswap_bitreverse_i16(i16 %a) nounwind {
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 48
; RV64ZBKB-NEXT: ret
+;
+; RV32ZBP-LABEL: test_bswap_bitreverse_i16:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev.b a0, a0
+; RV32ZBP-NEXT: ret
+;
+; RV64ZBP-LABEL: test_bswap_bitreverse_i16:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev.b a0, a0
+; RV64ZBP-NEXT: ret
%tmp = call i16 @llvm.bswap.i16(i16 %a)
%tmp2 = call i16 @llvm.bitreverse.i16(i16 %tmp)
ret i16 %tmp2
@@ -983,6 +1071,16 @@ define i32 @test_bswap_bitreverse_i32(i32 %a) nounwind {
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 32
; RV64ZBKB-NEXT: ret
+;
+; RV32ZBP-LABEL: test_bswap_bitreverse_i32:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev.b a0, a0
+; RV32ZBP-NEXT: ret
+;
+; RV64ZBP-LABEL: test_bswap_bitreverse_i32:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev.b a0, a0
+; RV64ZBP-NEXT: ret
%tmp = call i32 @llvm.bswap.i32(i32 %a)
%tmp2 = call i32 @llvm.bitreverse.i32(i32 %tmp)
ret i32 %tmp2
@@ -1129,6 +1227,17 @@ define i64 @test_bswap_bitreverse_i64(i64 %a) nounwind {
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: ret
+;
+; RV32ZBP-LABEL: test_bswap_bitreverse_i64:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev.b a0, a0
+; RV32ZBP-NEXT: rev.b a1, a1
+; RV32ZBP-NEXT: ret
+;
+; RV64ZBP-LABEL: test_bswap_bitreverse_i64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev.b a0, a0
+; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.bswap.i64(i64 %a)
%tmp2 = call i64 @llvm.bitreverse.i64(i64 %tmp)
ret i64 %tmp2
@@ -1253,6 +1362,16 @@ define i16 @test_bitreverse_bswap_i16(i16 %a) nounwind {
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 48
; RV64ZBKB-NEXT: ret
+;
+; RV32ZBP-LABEL: test_bitreverse_bswap_i16:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev.b a0, a0
+; RV32ZBP-NEXT: ret
+;
+; RV64ZBP-LABEL: test_bitreverse_bswap_i16:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev.b a0, a0
+; RV64ZBP-NEXT: ret
%tmp = call i16 @llvm.bitreverse.i16(i16 %a)
%tmp2 = call i16 @llvm.bswap.i16(i16 %tmp)
ret i16 %tmp2
@@ -1373,6 +1492,16 @@ define i32 @test_bitreverse_bswap_i32(i32 %a) nounwind {
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 32
; RV64ZBKB-NEXT: ret
+;
+; RV32ZBP-LABEL: test_bitreverse_bswap_i32:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev.b a0, a0
+; RV32ZBP-NEXT: ret
+;
+; RV64ZBP-LABEL: test_bitreverse_bswap_i32:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev.b a0, a0
+; RV64ZBP-NEXT: ret
%tmp = call i32 @llvm.bitreverse.i32(i32 %a)
%tmp2 = call i32 @llvm.bswap.i32(i32 %tmp)
ret i32 %tmp2
@@ -1519,6 +1648,17 @@ define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind {
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: ret
+;
+; RV32ZBP-LABEL: test_bitreverse_bswap_i64:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev.b a0, a0
+; RV32ZBP-NEXT: rev.b a1, a1
+; RV32ZBP-NEXT: ret
+;
+; RV64ZBP-LABEL: test_bitreverse_bswap_i64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev.b a0, a0
+; RV64ZBP-NEXT: ret
%tmp = call i64 @llvm.bitreverse.i64(i64 %a)
%tmp2 = call i64 @llvm.bswap.i64(i64 %tmp)
ret i64 %tmp2
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