[PATCH] D121496: [TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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The mask being NoRegister prevented the existing aliases from matching
since NoRegister isn't in the VMV0 register class.

To workaround this I've added new aliases that look for zero_reg.
I had to motify tablegen to generate matching code for zero_reg.
And as a consequence, I had to change the EmitPriority for an ARM
alias that used zero_reg that started printing.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121496

Files:
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
  llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
  llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll
  llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
  llvm/test/MC/RISCV/rvv/add.s
  llvm/test/MC/RISCV/rvv/xor.s
  llvm/utils/TableGen/AsmWriterEmitter.cpp

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