[PATCH] D113700: [AArch64] Improve costs for some conversions to fp16.
Florian Hahn via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 11 02:28:20 PST 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
fhahn marked an inline comment as done.
Closed by commit rGaa590e5823c3: [AArch64] Improve costs for some conversions to fp16. (authored by fhahn).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D113700/new/
https://reviews.llvm.org/D113700
Files:
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/AArch64/cast.ll
Index: llvm/test/Analysis/CostModel/AArch64/cast.ll
===================================================================
--- llvm/test/Analysis/CostModel/AArch64/cast.ll
+++ llvm/test/Analysis/CostModel/AArch64/cast.ll
@@ -1107,8 +1107,8 @@
; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 70 for instruction: %r159 = fptosi <16 x half> undef to <16 x i64>
; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r250 = uitofp <8 x i1> undef to <8 x half>
; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r251 = sitofp <8 x i1> undef to <8 x half>
-; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r252 = uitofp <8 x i8> undef to <8 x half>
-; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r253 = sitofp <8 x i8> undef to <8 x half>
+; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r252 = uitofp <8 x i8> undef to <8 x half>
+; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r253 = sitofp <8 x i8> undef to <8 x half>
; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r254 = uitofp <8 x i16> undef to <8 x half>
; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r255 = sitofp <8 x i16> undef to <8 x half>
; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r256 = uitofp <8 x i32> undef to <8 x half>
@@ -1117,8 +1117,8 @@
; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r259 = sitofp <8 x i64> undef to <8 x half>
; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r260 = uitofp <16 x i1> undef to <16 x half>
; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r261 = sitofp <16 x i1> undef to <16 x half>
-; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r262 = uitofp <16 x i8> undef to <16 x half>
-; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r263 = sitofp <16 x i8> undef to <16 x half>
+; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r262 = uitofp <16 x i8> undef to <16 x half>
+; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r263 = sitofp <16 x i8> undef to <16 x half>
; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r264 = uitofp <16 x i16> undef to <16 x half>
; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r265 = sitofp <16 x i16> undef to <16 x half>
; CHECK-FP16-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %r266 = uitofp <16 x i32> undef to <16 x half>
Index: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -1627,6 +1627,10 @@
{ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f16, 2},
{ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f16, 8}, // 4*fcvtl+4*fcvtzs
{ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f16, 8},
+ {ISD::UINT_TO_FP, MVT::v8f16, MVT::v8i8, 2}, // ushll + ucvtf
+ {ISD::SINT_TO_FP, MVT::v8f16, MVT::v8i8, 2}, // sshll + scvtf
+ {ISD::UINT_TO_FP, MVT::v16f16, MVT::v16i8, 4}, // 2 * ushl(2) + 2 * ucvtf
+ {ISD::SINT_TO_FP, MVT::v16f16, MVT::v16i8, 4}, // 2 * sshl(2) + 2 * scvtf
};
if (ST->hasFullFP16())
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