[PATCH] D121401: [AMDGPU] Support gfx940 v_lshl_add_u64 instruction

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/VOP3Instructions.td:689
+  (ThreeOpFrag<shl_0_to_4, add> i64:$src0, i32:$src1, i64:$src2),
+  (V_LSHL_ADD_U64_e64 VSrc_b64:$src0, VSrc_b32:$src1, VSrc_b64:$src2)
+>;
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If this is a normal VOP3 then surely src1 can be anything, so why restrict it to immediates 0..4 ? If this is a real restriction on the allowed operands, then you should probably mention that where the instruction is defined.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121401/new/

https://reviews.llvm.org/D121401