[PATCH] D121449: [AArch64] Combine ISD::SETCC into AArch64ISD::ANDS

[chenglin.bi via Phabricator via llvm-commits]

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When N > 12,  (2^N -1) is not a legal add immediate (isLegalAddImmediate will return false).
ANd if SetCC input use this number, DAG combiner will generate one more SRL instruction.
This change use TST to optimize the case.

Fix #54283


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121449

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/arm64-xaluo.ll

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