[PATCH] D121448: [DAGCombine] fold (bitreverse(srl (bitreverse c), x)) -> (shl c, x)

[Chenbing.Zheng via Phabricator via llvm-commits]

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Combine
t2 = bitreverse t1; t3 = srl t2, x; bitreverse t3 to shl t1, x.

This is similar to D120648 <https://reviews.llvm.org/D120648>,  and there is no limit to x %8 == 0
because of bitreverse is deal with one bit.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121448

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/RISCV/bitreverse-srli-bitreverse.ll
  llvm/test/CodeGen/X86/combine-bitreverse.ll

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