[PATCH] D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction
ShihPo Hung via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 11 00:09:09 PST 2022
arcbbb updated this revision to Diff 414599.
arcbbb edited the summary of this revision.
arcbbb added a comment.
Updates:
1. Add isUInt<2> check for timm.
2. Use 0 as round mode value in tests
3. Add tu and rv32 test cases.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D121376/new/
https://reviews.llvm.org/D121376
Files:
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/CMakeLists.txt
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCV.h
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
llvm/lib/Target/RISCV/RISCVSystemOperands.td
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/lib/Target/RISCV/RISCVVXRMRegister.cpp
llvm/test/CodeGen/RISCV/rvv/roundmode-insert.ll
llvm/test/CodeGen/RISCV/rvv/roundmode-insert.mir
llvm/test/CodeGen/RISCV/rvv/vaadd-rm-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vaadd-rm-rv64.ll
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