[llvm] db52256 - [X86] Add (u)comiss/sd tests showing eflags handling (PR38960)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 10 13:00:09 PST 2022
Author: Simon Pilgrim
Date: 2022-03-10T20:59:52Z
New Revision: db522568d5eb5b736e2079892d603c984106f9f9
URL: https://github.com/llvm/llvm-project/commit/db522568d5eb5b736e2079892d603c984106f9f9
DIFF: https://github.com/llvm/llvm-project/commit/db522568d5eb5b736e2079892d603c984106f9f9.diff
LOG: [X86] Add (u)comiss/sd tests showing eflags handling (PR38960)
Added:
llvm/test/CodeGen/X86/comi-flags.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/comi-flags.ll b/llvm/test/CodeGen/X86/comi-flags.ll
new file mode 100644
index 0000000000000..fc7ad817cf651
--- /dev/null
+++ b/llvm/test/CodeGen/X86/comi-flags.ll
@@ -0,0 +1,637 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefix=AVX
+
+;
+; SSE
+;
+
+define i32 @test_x86_sse_comieq_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse_comieq_ss:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: comiss %xmm1, %xmm0
+; SSE-NEXT: setnp %cl
+; SSE-NEXT: sete %dl
+; SSE-NEXT: andb %cl, %dl
+; SSE-NEXT: movzbl %dl, %ecx
+; SSE-NEXT: testl %ecx, %ecx
+; SSE-NEXT: cmovnel %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse_comieq_ss:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vcomiss %xmm1, %xmm0
+; AVX-NEXT: setnp %cl
+; AVX-NEXT: sete %dl
+; AVX-NEXT: andb %cl, %dl
+; AVX-NEXT: movzbl %dl, %ecx
+; AVX-NEXT: testl %ecx, %ecx
+; AVX-NEXT: cmovnel %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse.comieq.ss(<4 x float> %a0, <4 x float> %a1)
+ %cmp = icmp eq i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse.comieq.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define i32 @test_x86_sse_comige_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse_comige_ss:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: comiss %xmm1, %xmm0
+; SSE-NEXT: cmovbl %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse_comige_ss:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vcomiss %xmm1, %xmm0
+; AVX-NEXT: cmovbl %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse.comige.ss(<4 x float> %a0, <4 x float> %a1)
+ %cmp = icmp ne i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse.comige.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define i32 @test_x86_sse_comigt_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse_comigt_ss:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: comiss %xmm1, %xmm0
+; SSE-NEXT: cmoval %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse_comigt_ss:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vcomiss %xmm1, %xmm0
+; AVX-NEXT: cmoval %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse.comigt.ss(<4 x float> %a0, <4 x float> %a1)
+ %cmp = icmp eq i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse.comigt.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse_comile_ss:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: comiss %xmm0, %xmm1
+; SSE-NEXT: cmovbl %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse_comile_ss:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vcomiss %xmm0, %xmm1
+; AVX-NEXT: cmovbl %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x float> %a1)
+ %cmp = icmp ne i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse.comile.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define i32 @test_x86_sse_comilt_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse_comilt_ss:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: comiss %xmm0, %xmm1
+; SSE-NEXT: cmoval %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse_comilt_ss:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vcomiss %xmm0, %xmm1
+; AVX-NEXT: cmoval %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse.comilt.ss(<4 x float> %a0, <4 x float> %a1)
+ %cmp = icmp eq i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse.comilt.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define i32 @test_x86_sse_comineq_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse_comineq_ss:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: comiss %xmm1, %xmm0
+; SSE-NEXT: setp %cl
+; SSE-NEXT: setne %dl
+; SSE-NEXT: orb %cl, %dl
+; SSE-NEXT: movzbl %dl, %ecx
+; SSE-NEXT: testl %ecx, %ecx
+; SSE-NEXT: cmovel %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse_comineq_ss:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vcomiss %xmm1, %xmm0
+; AVX-NEXT: setp %cl
+; AVX-NEXT: setne %dl
+; AVX-NEXT: orb %cl, %dl
+; AVX-NEXT: movzbl %dl, %ecx
+; AVX-NEXT: testl %ecx, %ecx
+; AVX-NEXT: cmovel %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse.comineq.ss(<4 x float> %a0, <4 x float> %a1)
+ %cmp = icmp ne i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse.comineq.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define i32 @test_x86_sse_ucomieq_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse_ucomieq_ss:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: ucomiss %xmm1, %xmm0
+; SSE-NEXT: setnp %cl
+; SSE-NEXT: sete %dl
+; SSE-NEXT: andb %cl, %dl
+; SSE-NEXT: movzbl %dl, %ecx
+; SSE-NEXT: testl %ecx, %ecx
+; SSE-NEXT: cmovnel %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse_ucomieq_ss:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vucomiss %xmm1, %xmm0
+; AVX-NEXT: setnp %cl
+; AVX-NEXT: sete %dl
+; AVX-NEXT: andb %cl, %dl
+; AVX-NEXT: movzbl %dl, %ecx
+; AVX-NEXT: testl %ecx, %ecx
+; AVX-NEXT: cmovnel %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %a0, <4 x float> %a1)
+ %cmp = icmp eq i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse.ucomieq.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define i32 @test_x86_sse_ucomige_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse_ucomige_ss:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: ucomiss %xmm1, %xmm0
+; SSE-NEXT: cmovbl %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse_ucomige_ss:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vucomiss %xmm1, %xmm0
+; AVX-NEXT: cmovbl %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %a0, <4 x float> %a1)
+ %cmp = icmp ne i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define i32 @test_x86_sse_ucomigt_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse_ucomigt_ss:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: ucomiss %xmm1, %xmm0
+; SSE-NEXT: cmoval %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse_ucomigt_ss:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vucomiss %xmm1, %xmm0
+; AVX-NEXT: cmoval %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %a0, <4 x float> %a1)
+ %cmp = icmp eq i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse.ucomigt.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse_ucomile_ss:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: ucomiss %xmm0, %xmm1
+; SSE-NEXT: cmovbl %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse_ucomile_ss:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vucomiss %xmm0, %xmm1
+; AVX-NEXT: cmovbl %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x float> %a1)
+ %cmp = icmp ne i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse.ucomile.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define i32 @test_x86_sse_ucomilt_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse_ucomilt_ss:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: ucomiss %xmm0, %xmm1
+; SSE-NEXT: cmoval %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse_ucomilt_ss:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vucomiss %xmm0, %xmm1
+; AVX-NEXT: cmoval %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %a0, <4 x float> %a1)
+ %cmp = icmp eq i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse.ucomilt.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define i32 @test_x86_sse_ucomineq_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse_ucomineq_ss:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: ucomiss %xmm1, %xmm0
+; SSE-NEXT: setp %cl
+; SSE-NEXT: setne %dl
+; SSE-NEXT: orb %cl, %dl
+; SSE-NEXT: movzbl %dl, %ecx
+; SSE-NEXT: testl %ecx, %ecx
+; SSE-NEXT: cmovel %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse_ucomineq_ss:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vucomiss %xmm1, %xmm0
+; AVX-NEXT: setp %cl
+; AVX-NEXT: setne %dl
+; AVX-NEXT: orb %cl, %dl
+; AVX-NEXT: movzbl %dl, %ecx
+; AVX-NEXT: testl %ecx, %ecx
+; AVX-NEXT: cmovel %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> %a0, <4 x float> %a1)
+ %cmp = icmp ne i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse.ucomineq.ss(<4 x float>, <4 x float>) nounwind readnone
+
+;
+; SSE2
+;
+
+define i32 @test_x86_sse2_comieq_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse2_comieq_sd:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: comisd %xmm1, %xmm0
+; SSE-NEXT: setnp %cl
+; SSE-NEXT: sete %dl
+; SSE-NEXT: andb %cl, %dl
+; SSE-NEXT: movzbl %dl, %ecx
+; SSE-NEXT: testl %ecx, %ecx
+; SSE-NEXT: cmovnel %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse2_comieq_sd:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vcomisd %xmm1, %xmm0
+; AVX-NEXT: setnp %cl
+; AVX-NEXT: sete %dl
+; AVX-NEXT: andb %cl, %dl
+; AVX-NEXT: movzbl %dl, %ecx
+; AVX-NEXT: testl %ecx, %ecx
+; AVX-NEXT: cmovnel %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
+ %cmp = icmp eq i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define i32 @test_x86_sse2_comige_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse2_comige_sd:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: comisd %xmm1, %xmm0
+; SSE-NEXT: cmovbl %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse2_comige_sd:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vcomisd %xmm1, %xmm0
+; AVX-NEXT: cmovbl %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
+ %cmp = icmp ne i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse2.comige.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define i32 @test_x86_sse2_comigt_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse2_comigt_sd:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: comisd %xmm1, %xmm0
+; SSE-NEXT: cmoval %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse2_comigt_sd:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vcomisd %xmm1, %xmm0
+; AVX-NEXT: cmoval %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
+ %cmp = icmp eq i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse2.comigt.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse2_comile_sd:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: comisd %xmm0, %xmm1
+; SSE-NEXT: cmovbl %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse2_comile_sd:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vcomisd %xmm0, %xmm1
+; AVX-NEXT: cmovbl %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse2.comile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
+ %cmp = icmp ne i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse2.comile.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define i32 @test_x86_sse2_comilt_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse2_comilt_sd:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: comisd %xmm0, %xmm1
+; SSE-NEXT: cmoval %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse2_comilt_sd:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vcomisd %xmm0, %xmm1
+; AVX-NEXT: cmoval %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse2.comilt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
+ %cmp = icmp eq i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse2.comilt.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define i32 @test_x86_sse2_comineq_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse2_comineq_sd:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: comisd %xmm1, %xmm0
+; SSE-NEXT: setp %cl
+; SSE-NEXT: setne %dl
+; SSE-NEXT: orb %cl, %dl
+; SSE-NEXT: movzbl %dl, %ecx
+; SSE-NEXT: testl %ecx, %ecx
+; SSE-NEXT: cmovel %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse2_comineq_sd:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vcomisd %xmm1, %xmm0
+; AVX-NEXT: setp %cl
+; AVX-NEXT: setne %dl
+; AVX-NEXT: orb %cl, %dl
+; AVX-NEXT: movzbl %dl, %ecx
+; AVX-NEXT: testl %ecx, %ecx
+; AVX-NEXT: cmovel %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse2.comineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
+ %cmp = icmp ne i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse2.comineq.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define i32 @test_x86_sse2_ucomieq_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse2_ucomieq_sd:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: ucomisd %xmm1, %xmm0
+; SSE-NEXT: setnp %cl
+; SSE-NEXT: sete %dl
+; SSE-NEXT: andb %cl, %dl
+; SSE-NEXT: movzbl %dl, %ecx
+; SSE-NEXT: testl %ecx, %ecx
+; SSE-NEXT: cmovnel %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse2_ucomieq_sd:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vucomisd %xmm1, %xmm0
+; AVX-NEXT: setnp %cl
+; AVX-NEXT: sete %dl
+; AVX-NEXT: andb %cl, %dl
+; AVX-NEXT: movzbl %dl, %ecx
+; AVX-NEXT: testl %ecx, %ecx
+; AVX-NEXT: cmovnel %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
+ %cmp = icmp eq i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse2.ucomieq.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define i32 @test_x86_sse2_ucomige_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse2_ucomige_sd:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: ucomisd %xmm1, %xmm0
+; SSE-NEXT: cmovbl %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse2_ucomige_sd:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vucomisd %xmm1, %xmm0
+; AVX-NEXT: cmovbl %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
+ %cmp = icmp ne i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse2.ucomige.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define i32 @test_x86_sse2_ucomigt_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse2_ucomigt_sd:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: ucomisd %xmm1, %xmm0
+; SSE-NEXT: cmoval %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse2_ucomigt_sd:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vucomisd %xmm1, %xmm0
+; AVX-NEXT: cmoval %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
+ %cmp = icmp eq i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse2.ucomigt.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define i32 @test_x86_sse2_ucomile_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse2_ucomile_sd:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: ucomisd %xmm0, %xmm1
+; SSE-NEXT: cmovbl %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse2_ucomile_sd:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vucomisd %xmm0, %xmm1
+; AVX-NEXT: cmovbl %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
+ %cmp = icmp ne i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse2.ucomile.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define i32 @test_x86_sse2_ucomilt_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse2_ucomilt_sd:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: ucomisd %xmm0, %xmm1
+; SSE-NEXT: cmoval %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse2_ucomilt_sd:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vucomisd %xmm0, %xmm1
+; AVX-NEXT: cmoval %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse2.ucomilt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
+ %cmp = icmp eq i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse2.ucomilt.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define i32 @test_x86_sse2_ucomineq_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
+; SSE-LABEL: test_x86_sse2_ucomineq_sd:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: ucomisd %xmm1, %xmm0
+; SSE-NEXT: setp %cl
+; SSE-NEXT: setne %dl
+; SSE-NEXT: orb %cl, %dl
+; SSE-NEXT: movzbl %dl, %ecx
+; SSE-NEXT: testl %ecx, %ecx
+; SSE-NEXT: cmovel %esi, %eax
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_x86_sse2_ucomineq_sd:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vucomisd %xmm1, %xmm0
+; AVX-NEXT: setp %cl
+; AVX-NEXT: setne %dl
+; AVX-NEXT: orb %cl, %dl
+; AVX-NEXT: movzbl %dl, %ecx
+; AVX-NEXT: testl %ecx, %ecx
+; AVX-NEXT: cmovel %esi, %eax
+; AVX-NEXT: retq
+ %call = call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
+ %cmp = icmp ne i32 %call, 0
+ %res = select i1 %cmp, i32 %a2, i32 %a3
+ ret i32 %res
+}
+declare i32 @llvm.x86.sse2.ucomineq.sd(<2 x double>, <2 x double>) nounwind readnone
+
+define void @PR38960(<4 x float> %A, <4 x float> %B) {
+; SSE-LABEL: PR38960:
+; SSE: # %bb.0: # %entry
+; SSE-NEXT: comiss %xmm1, %xmm0
+; SSE-NEXT: setnp %al
+; SSE-NEXT: sete %cl
+; SSE-NEXT: andb %al, %cl
+; SSE-NEXT: movzbl %cl, %eax
+; SSE-NEXT: testl %eax, %eax
+; SSE-NEXT: je .LBB24_1
+; SSE-NEXT: # %bb.2: # %if.then
+; SSE-NEXT: jmp foo at PLT # TAILCALL
+; SSE-NEXT: .LBB24_1: # %if.end
+; SSE-NEXT: retq
+;
+; AVX-LABEL: PR38960:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: vcomiss %xmm1, %xmm0
+; AVX-NEXT: setnp %al
+; AVX-NEXT: sete %cl
+; AVX-NEXT: andb %al, %cl
+; AVX-NEXT: movzbl %cl, %eax
+; AVX-NEXT: testl %eax, %eax
+; AVX-NEXT: je .LBB24_1
+; AVX-NEXT: # %bb.2: # %if.then
+; AVX-NEXT: jmp foo at PLT # TAILCALL
+; AVX-NEXT: .LBB24_1: # %if.end
+; AVX-NEXT: retq
+entry:
+ %call = tail call i32 @llvm.x86.sse.comieq.ss(<4 x float> %A, <4 x float> %B) #3
+ %cmp = icmp eq i32 %call, 0
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then:
+ tail call void @foo()
+ br label %if.end
+
+if.end:
+ ret void
+}
+declare void @foo()
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