[PATCH] D121391: [AMDGPU] Use subreg encoding instead of reassign
Joe Nash via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 10 10:13:04 PST 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc8e6d68a9f15: [AMDGPU] Use subreg encoding instead of reassign (authored by Joe_Nash).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D121391/new/
https://reviews.llvm.org/D121391
Files:
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
Index: llvm/lib/Target/AMDGPU/SIRegisterInfo.td
===================================================================
--- llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -189,7 +189,7 @@
def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> {
let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1];
- let HWEncoding = 106;
+ let HWEncoding = VCC_LO.HWEncoding;
}
defm EXEC_LO : SIRegLoHi16<"exec_lo", 126>, DwarfRegNum<[1, 1]>;
@@ -198,7 +198,7 @@
def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]> {
let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1];
- let HWEncoding = 126;
+ let HWEncoding = EXEC_LO.HWEncoding;
}
// 32-bit real registers, for MC only.
@@ -237,7 +237,7 @@
RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]> {
let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1];
- let HWEncoding = 104;
+ let HWEncoding = XNACK_MASK_LO.HWEncoding;
}
// Trap handler registers
@@ -247,7 +247,7 @@
def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]> {
let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1];
- let HWEncoding = 108;
+ let HWEncoding = TBA_LO.HWEncoding;
}
defm TMA_LO : SIRegLoHi16<"tma_lo", 110>;
@@ -256,7 +256,7 @@
def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]> {
let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1];
- let HWEncoding = 110;
+ let HWEncoding = TMA_LO.HWEncoding;
}
foreach Index = 0...15 in {
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