[PATCH] D120912: [AArch64][SVE] Convert gather/scatter with a stride of 2 to contiguous loads/stores

Thu Mar 10 05:59:15 PST 2022

kmclaughlin added inline comments.

================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16614
+  else
+    return SDValue();
+
----------------
david-arm wrote:
> I think you may need some extra checks here for extending gather loads or truncating scatter stores and bail out for both cases, otherwise we may attempt to do the DAG combine for extloads of nxv4i32 -> nx4i64.
I think in the case of extending gather loads and truncating scatter stores, the index opcode would be a sign/zero-extend or trunc instead of a stepvector? I've added some tests to check that we don't perform the combine in these cases.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120912/new/

https://reviews.llvm.org/D120912