[llvm] b1e513a - [PhaseOrdering][x86] add TODO comments to test files; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2022-03-10T08:10:28-05:00
New Revision: b1e513ae8e25d379f21c7d1124524611ee59b253

URL: https://github.com/llvm/llvm-project/commit/b1e513ae8e25d379f21c7d1124524611ee59b253
DIFF: https://github.com/llvm/llvm-project/commit/b1e513ae8e25d379f21c7d1124524611ee59b253.diff

LOG: [PhaseOrdering][x86] add TODO comments to test files; NFC

The intended folds were removed because an underlying
analysis was not correct ( b48fe158e0a8 ).

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/vec_minmax_match.ll
    llvm/test/Transforms/PhaseOrdering/min-max-abs-cse.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/vec_minmax_match.ll b/llvm/test/CodeGen/X86/vec_minmax_match.ll
index c963bad07d1a0..56a45fa9a4ff5 100644
--- a/llvm/test/CodeGen/X86/vec_minmax_match.ll
+++ b/llvm/test/CodeGen/X86/vec_minmax_match.ll
@@ -30,8 +30,10 @@ define <4 x i32> @smin_vec2(<4 x i32> %x) {
   ret <4 x i32> %sel
 }
 
-; Z = X -nsw Y
-; (X >s Y) ? 0 : Z ==> (Z >s 0) ? 0 : Z ==> SMIN(Z, 0)
+; TODO:
+; This and the next test were intended to become smin,
+; but that is not correct in general.
+
 define <4 x i32> @smin_vec3(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: smin_vec3:
 ; CHECK:       # %bb.0:
@@ -45,8 +47,6 @@ define <4 x i32> @smin_vec3(<4 x i32> %x, <4 x i32> %y) {
   ret <4 x i32> %sel
 }
 
-; Z = X -nsw Y
-; (X <s Y) ? Z : 0 ==> (Z <s 0) ? Z : 0 ==> SMIN(Z, 0)
 define <4 x i32> @smin_vec4(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: smin_vec4:
 ; CHECK:       # %bb.0:
@@ -86,8 +86,10 @@ define <4 x i32> @smax_vec2(<4 x i32> %x) {
   ret <4 x i32> %sel
 }
 
-; Z = X -nsw Y
-; (X <s Y) ? 0 : Z ==> (Z <s 0) ? 0 : Z ==> SMAX(Z, 0)
+; TODO:
+; This and the next test were intended to become smax,
+; but that is not correct in general.
+
 define <4 x i32> @smax_vec3(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: smax_vec3:
 ; CHECK:       # %bb.0:
@@ -101,8 +103,6 @@ define <4 x i32> @smax_vec3(<4 x i32> %x, <4 x i32> %y) {
   ret <4 x i32> %sel
 }
 
-; Z = X -nsw Y
-; (X >s Y) ? Z : 0 ==> (Z >s 0) ? Z : 0 ==> SMAX(Z, 0)
 define <4 x i32> @smax_vec4(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: smax_vec4:
 ; CHECK:       # %bb.0:

diff  --git a/llvm/test/Transforms/PhaseOrdering/min-max-abs-cse.ll b/llvm/test/Transforms/PhaseOrdering/min-max-abs-cse.ll
index 2f3dd4b291de2..b7e16cf086014 100644
--- a/llvm/test/Transforms/PhaseOrdering/min-max-abs-cse.ll
+++ b/llvm/test/Transforms/PhaseOrdering/min-max-abs-cse.ll
@@ -5,7 +5,9 @@
 ; In all tests, expect instcombine to canonicalize the select patterns
 ; for min/max/abs to allow CSE and subsequent simplification.
 
-; sub (smax a,b), (smax a,b) --> 0
+; TODO:
+; This should be reduced to 0, but we are missing some
+; fold(s) in instcombine.
 
 define i8 @smax_nsw(i8 %a, i8 %b) {
 ; CHECK-LABEL: @smax_nsw(