[llvm] d537075 - [RISCV] Remove RISCVISD::VLE_VL/VSE_VL. Use intrinsics instead.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 9 22:57:16 PST 2022
Author: Craig Topper
Date: 2022-03-09T22:44:28-08:00
New Revision: d53707508a7af8bc5f2fe785ee959273027cdce4
URL: https://github.com/llvm/llvm-project/commit/d53707508a7af8bc5f2fe785ee959273027cdce4
DIFF: https://github.com/llvm/llvm-project/commit/d53707508a7af8bc5f2fe785ee959273027cdce4.diff
LOG: [RISCV] Remove RISCVISD::VLE_VL/VSE_VL. Use intrinsics instead.
Similar to what we do for other loads/stores, use the intrinsic
version that we already have custom isel for.
Reviewed By: rogfer01
Differential Revision: https://reviews.llvm.org/D121166
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index cd7318f79f3d2..589c26cc0ba5b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -5664,15 +5664,23 @@ RISCVTargetLowering::lowerFixedLengthVectorLoadToRVV(SDValue Op,
"Expecting a correctly-aligned load");
MVT VT = Op.getSimpleValueType();
+ MVT XLenVT = Subtarget.getXLenVT();
MVT ContainerVT = getContainerForFixedLengthVector(VT);
- SDValue VL =
- DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT());
+ SDValue VL = DAG.getConstant(VT.getVectorNumElements(), DL, XLenVT);
+ bool IsMaskOp = VT.getVectorElementType() == MVT::i1;
+ SDValue IntID = DAG.getTargetConstant(
+ IsMaskOp ? Intrinsic::riscv_vlm : Intrinsic::riscv_vle, DL, XLenVT);
+ SmallVector<SDValue, 4> Ops{Load->getChain(), IntID};
+ if (!IsMaskOp)
+ Ops.push_back(DAG.getUNDEF(ContainerVT));
+ Ops.push_back(Load->getBasePtr());
+ Ops.push_back(VL);
SDVTList VTs = DAG.getVTList({ContainerVT, MVT::Other});
- SDValue NewLoad = DAG.getMemIntrinsicNode(
- RISCVISD::VLE_VL, DL, VTs, {Load->getChain(), Load->getBasePtr(), VL},
- Load->getMemoryVT(), Load->getMemOperand());
+ SDValue NewLoad =
+ DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops,
+ Load->getMemoryVT(), Load->getMemOperand());
SDValue Result = convertFromScalableVector(VT, NewLoad, DAG, Subtarget);
return DAG.getMergeValues({Result, Load->getChain()}, DL);
@@ -5691,6 +5699,7 @@ RISCVTargetLowering::lowerFixedLengthVectorStoreToRVV(SDValue Op,
SDValue StoreVal = Store->getValue();
MVT VT = StoreVal.getSimpleValueType();
+ MVT XLenVT = Subtarget.getXLenVT();
// If the size less than a byte, we need to pad with zeros to make a byte.
if (VT.getVectorElementType() == MVT::i1 && VT.getVectorNumElements() < 8) {
@@ -5702,14 +5711,17 @@ RISCVTargetLowering::lowerFixedLengthVectorStoreToRVV(SDValue Op,
MVT ContainerVT = getContainerForFixedLengthVector(VT);
- SDValue VL =
- DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT());
+ SDValue VL = DAG.getConstant(VT.getVectorNumElements(), DL, XLenVT);
SDValue NewValue =
convertToScalableVector(ContainerVT, StoreVal, DAG, Subtarget);
+
+ bool IsMaskOp = VT.getVectorElementType() == MVT::i1;
+ SDValue IntID = DAG.getTargetConstant(
+ IsMaskOp ? Intrinsic::riscv_vsm : Intrinsic::riscv_vse, DL, XLenVT);
return DAG.getMemIntrinsicNode(
- RISCVISD::VSE_VL, DL, DAG.getVTList(MVT::Other),
- {Store->getChain(), NewValue, Store->getBasePtr(), VL},
+ ISD::INTRINSIC_VOID, DL, DAG.getVTList(MVT::Other),
+ {Store->getChain(), IntID, NewValue, Store->getBasePtr(), VL},
Store->getMemoryVT(), Store->getMemOperand());
}
@@ -10826,8 +10838,6 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(VSEXT_VL)
NODE_NAME_CASE(VZEXT_VL)
NODE_NAME_CASE(VCPOP_VL)
- NODE_NAME_CASE(VLE_VL)
- NODE_NAME_CASE(VSE_VL)
NODE_NAME_CASE(READ_CSR)
NODE_NAME_CASE(WRITE_CSR)
NODE_NAME_CASE(SWAP_CSR)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 18e9ef9e0e846..ab11602b6b621 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -311,10 +311,6 @@ enum NodeType : unsigned {
STRICT_FCVT_W_RV64 = ISD::FIRST_TARGET_STRICTFP_OPCODE,
STRICT_FCVT_WU_RV64,
- // Memory opcodes start here.
- VLE_VL = ISD::FIRST_TARGET_MEMORY_OPCODE,
- VSE_VL,
-
// WARNING: Do not add anything in the end unless you want the node to
// have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
// opcodes will be thought as target memory ops!
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 56e5a99fda6e6..8e5549bd5b22b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -21,11 +21,6 @@
// Helpers to define the VL patterns.
//===----------------------------------------------------------------------===//
-def SDT_RISCVVLE_VL : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisPtrTy<1>,
- SDTCisVT<2, XLenVT>]>;
-def SDT_RISCVVSE_VL : SDTypeProfile<0, 3, [SDTCisVec<0>, SDTCisPtrTy<1>,
- SDTCisVT<2, XLenVT>]>;
-
def SDT_RISCVIntBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>,
SDTCisVec<0>, SDTCisInt<0>,
@@ -66,11 +61,6 @@ def riscv_vfmv_s_f_vl : SDNode<"RISCVISD::VFMV_S_F_VL",
SDTCisEltOfVec<2, 0>,
SDTCisVT<3, XLenVT>]>>;
-def riscv_vle_vl : SDNode<"RISCVISD::VLE_VL", SDT_RISCVVLE_VL,
- [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
-def riscv_vse_vl : SDNode<"RISCVISD::VSE_VL", SDT_RISCVVSE_VL,
- [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
-
def riscv_add_vl : SDNode<"RISCVISD::ADD_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
def riscv_sub_vl : SDNode<"RISCVISD::SUB_VL", SDT_RISCVIntBinOp_VL>;
def riscv_mul_vl : SDNode<"RISCVISD::MUL_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
@@ -745,29 +735,6 @@ multiclass VPatWidenReductionVL_Ext_VL<SDNode vop, PatFrags extop, string instru
let Predicates = [HasVInstructions] in {
-// 7.4. Vector Unit-Stride Instructions
-foreach vti = AllVectors in {
- defvar load_instr = !cast<Instruction>("PseudoVLE"#vti.SEW#"_V_"#vti.LMul.MX);
- defvar store_instr = !cast<Instruction>("PseudoVSE"#vti.SEW#"_V_"#vti.LMul.MX);
- // Load
- def : Pat<(vti.Vector (riscv_vle_vl BaseAddr:$rs1, VLOpFrag)),
- (load_instr BaseAddr:$rs1, GPR:$vl, vti.Log2SEW)>;
- // Store
- def : Pat<(riscv_vse_vl (vti.Vector vti.RegClass:$rs2), BaseAddr:$rs1,
- VLOpFrag),
- (store_instr vti.RegClass:$rs2, BaseAddr:$rs1, GPR:$vl, vti.Log2SEW)>;
-}
-
-foreach mti = AllMasks in {
- defvar load_instr = !cast<Instruction>("PseudoVLM_V_"#mti.BX);
- defvar store_instr = !cast<Instruction>("PseudoVSM_V_"#mti.BX);
- def : Pat<(mti.Mask (riscv_vle_vl BaseAddr:$rs1, VLOpFrag)),
- (load_instr BaseAddr:$rs1, GPR:$vl, mti.Log2SEW)>;
- def : Pat<(riscv_vse_vl (mti.Mask VR:$rs2), BaseAddr:$rs1,
- VLOpFrag),
- (store_instr VR:$rs2, BaseAddr:$rs1, GPR:$vl, mti.Log2SEW)>;
-}
-
// 12.1. Vector Single-Width Integer Add and Subtract
defm : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">;
defm : VPatBinaryVL_VV_VX<riscv_sub_vl, "PseudoVSUB">;
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