[PATCH] D120899: [RISCV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 9 13:57:07 PST 2022
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4694
MVT I32MaskVT = MVT::getVectorVT(MVT::i1, I32VT.getVectorElementCount());
- SDValue I32Mask = DAG.getNode(RISCVISD::VMSET_VL, DL, I32MaskVT, VL);
+ SDValue I32Mask = DAG.getNode(RISCVISD::VMSET_VL, DL, I32MaskVT, AVL);
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This AVL should be I32VL to match the I32 type. It was wrong in the old code. It should have been scaled by 2. Since its gets pattern matched away during isel it probably doesn't really matter, but could to be logically correct.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D120899/new/
https://reviews.llvm.org/D120899
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