[PATCH] D121320: X86ISelDAGToDAG: Transform TEST + MOV64ri to SHR + TEST

[Matthias Braun via Phabricator via llvm-commits]

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Optimize a pattern where a sequence of 8/16 or 32 bits is tested for zero: LLVM normalizes this towards and `AND` with mask which is usually good, but does not work well on X86 when the mask does not fit into a 64bit register. This DagToDAG peephole transforms sequences like:

  movabsq $562941363486720, %rax # imm = 0x1FFFE00000000
  testq %rax, %rdi

to

  shrq $33, %rdi
  testw %di, %di

the result has a shorter encoding and saves a register if the tested value isn't used otherwise.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121320

Files:
  llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
  llvm/test/CodeGen/X86/dag-test-mov64ri.ll
  llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
  llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

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