[llvm] 3836003 - [AArch64] Add test for D120481 with multiple uses.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 8 03:11:17 PST 2022
Author: Florian Hahn
Date: 2022-03-08T11:11:03Z
New Revision: 3836003e87ee7c5975c52ecb6dbd2a68af6986df
URL: https://github.com/llvm/llvm-project/commit/3836003e87ee7c5975c52ecb6dbd2a68af6986df
DIFF: https://github.com/llvm/llvm-project/commit/3836003e87ee7c5975c52ecb6dbd2a68af6986df.diff
LOG: [AArch64] Add test for D120481 with multiple uses.
Added:
Modified:
llvm/test/CodeGen/AArch64/vselect-ext.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/vselect-ext.ll b/llvm/test/CodeGen/AArch64/vselect-ext.ll
index 3186df57ea55a..d9405b780e1d3 100644
--- a/llvm/test/CodeGen/AArch64/vselect-ext.ll
+++ b/llvm/test/CodeGen/AArch64/vselect-ext.ll
@@ -111,6 +111,62 @@ entry:
ret <16 x i32> %sel
}
+; A variation of @same_zext_used_in_cmp_unsigned_pred_and_select, with with
+; multiple users of the compare.
+define <16 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_other_use(<16 x i8> %a, <16 x i64> %v, <16 x i64>* %ptr) {
+; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_other_use:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: mov.16b v16, v2
+; CHECK-NEXT: movi.16b v2, #10
+; CHECK-NEXT: ushll.8h v18, v0, #0
+; CHECK-NEXT: ushll2.8h v20, v0, #0
+; CHECK-NEXT: mov.16b v17, v1
+; CHECK-NEXT: ldr q1, [sp]
+; CHECK-NEXT: cmhi.16b v0, v0, v2
+; CHECK-NEXT: ushll.4s v19, v18, #0
+; CHECK-NEXT: sshll2.8h v21, v0, #0
+; CHECK-NEXT: sshll.8h v0, v0, #0
+; CHECK-NEXT: sshll2.4s v22, v21, #0
+; CHECK-NEXT: sshll.4s v21, v21, #0
+; CHECK-NEXT: sshll2.2d v23, v22, #0
+; CHECK-NEXT: sshll.2d v24, v22, #0
+; CHECK-NEXT: sshll2.4s v25, v0, #0
+; CHECK-NEXT: sshll2.2d v26, v21, #0
+; CHECK-NEXT: sshll.2d v28, v21, #0
+; CHECK-NEXT: sshll2.2d v27, v25, #0
+; CHECK-NEXT: sshll.4s v0, v0, #0
+; CHECK-NEXT: and.16b v1, v1, v23
+; CHECK-NEXT: and.16b v7, v7, v24
+; CHECK-NEXT: sshll.2d v29, v25, #0
+; CHECK-NEXT: stp q7, q1, [x0, #96]
+; CHECK-NEXT: and.16b v1, v6, v26
+; CHECK-NEXT: and.16b v5, v5, v28
+; CHECK-NEXT: ushll.4s v2, v20, #0
+; CHECK-NEXT: stp q5, q1, [x0, #64]
+; CHECK-NEXT: ushll2.4s v18, v18, #0
+; CHECK-NEXT: ushll2.4s v20, v20, #0
+; CHECK-NEXT: and.16b v1, v4, v27
+; CHECK-NEXT: sshll2.2d v4, v0, #0
+; CHECK-NEXT: sshll.2d v5, v0, #0
+; CHECK-NEXT: and.16b v3, v3, v29
+; CHECK-NEXT: stp q3, q1, [x0, #32]
+; CHECK-NEXT: and.16b v3, v20, v22
+; CHECK-NEXT: and.16b v1, v18, v25
+; CHECK-NEXT: and.16b v2, v2, v21
+; CHECK-NEXT: and.16b v0, v19, v0
+; CHECK-NEXT: and.16b v4, v16, v4
+; CHECK-NEXT: and.16b v5, v17, v5
+; CHECK-NEXT: stp q5, q4, [x0]
+; CHECK-NEXT: ret
+entry:
+ %ext = zext <16 x i8> %a to <16 x i32>
+ %cmp = icmp ugt <16 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
+ %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer
+ %sel.2 = select <16 x i1> %cmp, <16 x i64> %v, <16 x i64> zeroinitializer
+ store <16 x i64> %sel.2, <16 x i64>* %ptr
+ ret <16 x i32> %sel
+}
+
define <16 x i32> @same_sext_used_in_cmp_signed_pred_and_select(<16 x i8> %a) {
; CHECK-LABEL: same_sext_used_in_cmp_signed_pred_and_select:
; CHECK: ; %bb.0: ; %entry
@@ -203,7 +259,7 @@ define void @extension_in_loop_v16i8_to_v16i32(i8* %src, i32* %dst) {
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: movi.2d v0, #0xffffffffffffffff
; CHECK-NEXT: mov x8, xzr
-; CHECK-NEXT: LBB7_1: ; %loop
+; CHECK-NEXT: LBB8_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q1, [x0, x8]
; CHECK-NEXT: add x8, x8, #16
@@ -227,7 +283,7 @@ define void @extension_in_loop_v16i8_to_v16i32(i8* %src, i32* %dst) {
; CHECK-NEXT: and.16b v3, v3, v4
; CHECK-NEXT: and.16b v1, v1, v2
; CHECK-NEXT: stp q1, q3, [x1], #64
-; CHECK-NEXT: b.ne LBB7_1
+; CHECK-NEXT: b.ne LBB8_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
entry:
@@ -256,25 +312,25 @@ define void @extension_in_loop_as_shuffle_v16i8_to_v16i32(i8* %src, i32* %dst) {
; CHECK-LABEL: extension_in_loop_as_shuffle_v16i8_to_v16i32:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: Lloh0:
-; CHECK-NEXT: adrp x9, lCPI8_0 at PAGE
+; CHECK-NEXT: adrp x9, lCPI9_0 at PAGE
; CHECK-NEXT: Lloh1:
-; CHECK-NEXT: adrp x10, lCPI8_1 at PAGE
+; CHECK-NEXT: adrp x10, lCPI9_1 at PAGE
; CHECK-NEXT: Lloh2:
-; CHECK-NEXT: adrp x11, lCPI8_2 at PAGE
+; CHECK-NEXT: adrp x11, lCPI9_2 at PAGE
; CHECK-NEXT: Lloh3:
-; CHECK-NEXT: adrp x12, lCPI8_3 at PAGE
+; CHECK-NEXT: adrp x12, lCPI9_3 at PAGE
; CHECK-NEXT: movi.2d v1, #0xffffffffffffffff
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: movi.2d v3, #0000000000000000
; CHECK-NEXT: Lloh4:
-; CHECK-NEXT: ldr q0, [x9, lCPI8_0 at PAGEOFF]
+; CHECK-NEXT: ldr q0, [x9, lCPI9_0 at PAGEOFF]
; CHECK-NEXT: Lloh5:
-; CHECK-NEXT: ldr q2, [x10, lCPI8_1 at PAGEOFF]
+; CHECK-NEXT: ldr q2, [x10, lCPI9_1 at PAGEOFF]
; CHECK-NEXT: Lloh6:
-; CHECK-NEXT: ldr q5, [x11, lCPI8_2 at PAGEOFF]
+; CHECK-NEXT: ldr q5, [x11, lCPI9_2 at PAGEOFF]
; CHECK-NEXT: Lloh7:
-; CHECK-NEXT: ldr q6, [x12, lCPI8_3 at PAGEOFF]
-; CHECK-NEXT: LBB8_1: ; %loop
+; CHECK-NEXT: ldr q6, [x12, lCPI9_3 at PAGEOFF]
+; CHECK-NEXT: LBB9_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q4, [x0, x8]
; CHECK-NEXT: add x8, x8, #16
@@ -296,7 +352,7 @@ define void @extension_in_loop_as_shuffle_v16i8_to_v16i32(i8* %src, i32* %dst) {
; CHECK-NEXT: and.16b v16, v18, v16
; CHECK-NEXT: and.16b v7, v19, v7
; CHECK-NEXT: stp q7, q16, [x1], #64
-; CHECK-NEXT: b.ne LBB8_1
+; CHECK-NEXT: b.ne LBB9_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh3, Lloh7
@@ -330,25 +386,25 @@ define void @shuffle_in_loop_is_no_extend_v16i8_to_v16i32(i8* %src, i32* %dst) {
; CHECK-LABEL: shuffle_in_loop_is_no_extend_v16i8_to_v16i32:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: Lloh8:
-; CHECK-NEXT: adrp x9, lCPI9_0 at PAGE
+; CHECK-NEXT: adrp x9, lCPI10_0 at PAGE
; CHECK-NEXT: Lloh9:
-; CHECK-NEXT: adrp x10, lCPI9_1 at PAGE
+; CHECK-NEXT: adrp x10, lCPI10_1 at PAGE
; CHECK-NEXT: Lloh10:
-; CHECK-NEXT: adrp x11, lCPI9_2 at PAGE
+; CHECK-NEXT: adrp x11, lCPI10_2 at PAGE
; CHECK-NEXT: Lloh11:
-; CHECK-NEXT: adrp x12, lCPI9_3 at PAGE
+; CHECK-NEXT: adrp x12, lCPI10_3 at PAGE
; CHECK-NEXT: movi.2d v2, #0000000000000000
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: movi.2d v5, #0xffffffffffffffff
; CHECK-NEXT: Lloh12:
-; CHECK-NEXT: ldr q0, [x9, lCPI9_0 at PAGEOFF]
+; CHECK-NEXT: ldr q0, [x9, lCPI10_0 at PAGEOFF]
; CHECK-NEXT: Lloh13:
-; CHECK-NEXT: ldr q4, [x10, lCPI9_1 at PAGEOFF]
+; CHECK-NEXT: ldr q4, [x10, lCPI10_1 at PAGEOFF]
; CHECK-NEXT: Lloh14:
-; CHECK-NEXT: ldr q6, [x11, lCPI9_2 at PAGEOFF]
+; CHECK-NEXT: ldr q6, [x11, lCPI10_2 at PAGEOFF]
; CHECK-NEXT: Lloh15:
-; CHECK-NEXT: ldr q7, [x12, lCPI9_3 at PAGEOFF]
-; CHECK-NEXT: LBB9_1: ; %loop
+; CHECK-NEXT: ldr q7, [x12, lCPI10_3 at PAGEOFF]
+; CHECK-NEXT: LBB10_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q1, [x0, x8]
; CHECK-NEXT: add x8, x8, #16
@@ -371,7 +427,7 @@ define void @shuffle_in_loop_is_no_extend_v16i8_to_v16i32(i8* %src, i32* %dst) {
; CHECK-NEXT: and.16b v17, v20, v23
; CHECK-NEXT: and.16b v16, v21, v16
; CHECK-NEXT: stp q16, q17, [x1], #64
-; CHECK-NEXT: b.ne LBB9_1
+; CHECK-NEXT: b.ne LBB10_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh11, Lloh15
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