[PATCH] D121113: [RISCV][VP] Custom lower VP_STRIDED_LOAD and VP_STRIDED_STORE

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6099
+  SDValue Result =
+      DAG.getMemIntrinsicNode(RISCVISD::VLSE_VL, DL, VTs,
+                              {VPNode->getChain(), VPNode->getBasePtr(), Stride,
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Should we be using INTRINSIC_W_CHAIN and intrinsic_riscv_vlse/vlse_mask similar to what we do for other VP load/store?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D121113/new/

https://reviews.llvm.org/D121113