[PATCH] D120899: [RISCV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h:381
+inline static unsigned encodeSEW(unsigned SEW) {
+  assert(isValidSEW(SEW) && "Unspected SEW value");
+  return Log2_32(SEW) - 3;
----------------
Unspected -> Unexpected


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vslide1-rv32.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -riscv-v-vector-bits-min=256 -riscv-v-vector-bits-max=256 \
----------------
There are no "fixed vectors" in this test. So I don't like this test name.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120899/new/

https://reviews.llvm.org/D120899