[PATCH] D121105: [NFC][LV] Use different braces in debug output

Roman Lebedev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Mar 7 08:33:14 PST 2022 

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2f80ea7f4f7e: [NFC][LV] Use different braces in debug output (authored by lebedev.ri).

Changed prior to commit:
  https://reviews.llvm.org/D121105?vs=413420&id=413498#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121105/new/

https://reviews.llvm.org/D121105

Files:
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  llvm/test/Analysis/CostModel/X86/gather-i16-with-i8-index.ll
  llvm/test/Analysis/CostModel/X86/gather-i32-with-i8-index.ll
  llvm/test/Analysis/CostModel/X86/gather-i64-with-i8-index.ll
  llvm/test/Analysis/CostModel/X86/gather-i8-with-i8-index.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-5.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2-indices-0u.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-01u.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-0uu.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-012u.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-01uu.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-0uuu.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-5.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-6.ll
  llvm/test/Analysis/CostModel/X86/masked-gather-i32-with-i8-index.ll
  llvm/test/Analysis/CostModel/X86/masked-gather-i64-with-i8-index.ll
  llvm/test/Analysis/CostModel/X86/masked-interleaved-load-i16.ll
  llvm/test/Analysis/CostModel/X86/masked-interleaved-store-i16.ll
  llvm/test/Analysis/CostModel/X86/masked-load-i16.ll
  llvm/test/Analysis/CostModel/X86/masked-load-i32.ll
  llvm/test/Analysis/CostModel/X86/masked-load-i64.ll
  llvm/test/Analysis/CostModel/X86/masked-load-i8.ll
  llvm/test/Analysis/CostModel/X86/masked-scatter-i32-with-i8-index.ll
  llvm/test/Analysis/CostModel/X86/masked-scatter-i64-with-i8-index.ll
  llvm/test/Analysis/CostModel/X86/masked-store-i16.ll
  llvm/test/Analysis/CostModel/X86/masked-store-i32.ll
  llvm/test/Analysis/CostModel/X86/masked-store-i64.ll
  llvm/test/Analysis/CostModel/X86/masked-store-i8.ll
  llvm/test/Analysis/CostModel/X86/scatter-i16-with-i8-index.ll
  llvm/test/Analysis/CostModel/X86/scatter-i32-with-i8-index.ll
  llvm/test/Analysis/CostModel/X86/scatter-i64-with-i8-index.ll
  llvm/test/Analysis/CostModel/X86/scatter-i8-with-i8-index.ll
  llvm/test/Transforms/LoopVectorize/AArch64/interleaved_cost.ll
  llvm/test/Transforms/LoopVectorize/AArch64/masked-op-cost.ll
  llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization.ll
  llvm/test/Transforms/LoopVectorize/AArch64/scalable-vf-hint.ll
  llvm/test/Transforms/LoopVectorize/AArch64/smallest-and-widest-types.ll
  llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
  llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter-cost.ll
  llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
  llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll
  llvm/test/Transforms/LoopVectorize/ARM/interleaved_cost.ll
  llvm/test/Transforms/LoopVectorize/ARM/mve-interleaved-cost.ll
  llvm/test/Transforms/LoopVectorize/SystemZ/mem-interleaving-costs-02.ll
  llvm/test/Transforms/LoopVectorize/X86/already-vectorized.ll
  llvm/test/Transforms/LoopVectorize/X86/reg-usage-debug.ll
  llvm/test/Transforms/LoopVectorize/X86/uniformshift.ll
  llvm/test/Transforms/LoopVectorize/X86/vector-scalar-select-cost.ll
  llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll
  llvm/test/Transforms/LoopVectorize/interleaved-accesses-masked-group.ll
  llvm/test/Transforms/LoopVectorize/loop-legality-checks.ll
  llvm/test/Transforms/LoopVectorize/nounroll.ll
  llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-limitations.ll
  llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-scalable.ll
  llvm/test/Transforms/LoopVectorize/pr39099.ll
  llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
  llvm/test/Transforms/LoopVectorize/vplan-printing.ll
  llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll

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