[llvm] 54dafd3 - [AArch64] Move FeatureSpecRestrict into core 8.0-R architecture.

[Simon Tatham via llvm-commits]

Author: Simon Tatham
Date: 2022-03-07T15:55:08Z
New Revision: 54dafd38c5c6f36e37b266f5f1a588ac11e6db5d

URL: https://github.com/llvm/llvm-project/commit/54dafd38c5c6f36e37b266f5f1a588ac11e6db5d
DIFF: https://github.com/llvm/llvm-project/commit/54dafd38c5c6f36e37b266f5f1a588ac11e6db5d.diff

LOG: [AArch64] Move FeatureSpecRestrict into core 8.0-R architecture.

It was included in HasV8_0rOps when D88660 first introduced that
architecture definition. In D118045 I moved it out of there and into
ProcessorFeatures.R82, so that -mcpu=cortex-r82 would continue to
behave the same as before but -march=armv8-r would include only the
mandatory parts of the architecture.

In fact, that was a mistake. Firstly, Cortex-R82 _doesn't_ implement
that feature, so it makes no sense to deliberately enable it for that
CPU in particular. But also, it's an extension that only adds system
registers, and we're generally more relaxed about where we enable
those (because kernel developers find it useful to write sysreg-access
instructions after runtime checking, and because sysreg accesses
aren't manufactured during code generation so the risk is small).

So, in line with that usual AArch64 policy, FeatureSpecRestrict ought
to be considered part of 8.0-R for LLVM purposes. So I'm moving it
back into HasV8_0rOps, where it started out.

Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D120830

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64.td
    llvm/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 89209b38e6726..f53218c35d46e 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -532,7 +532,11 @@ def HasV8_0rOps : SubtargetFeature<
   FeaturePAuth, FeatureRCPC,
   //v8.4
   FeatureDotProd, FeatureTRACEV8_4, FeatureTLB_RMI,
-  FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO]>;
+  FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO,
+  // Not mandatory in v8.0-R, but included here on the grounds that it
+  // only enables names of system registers
+  FeatureSpecRestrict
+  ]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
@@ -968,7 +972,7 @@ def ProcessorFeatures {
                                  FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8];
   list<SubtargetFeature> R82  = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16,
                                  FeatureFP16FML, FeatureSSBS, FeaturePredRes,
-                                 FeatureSB, FeatureSpecRestrict];
+                                 FeatureSB];
   list<SubtargetFeature> X1   = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
                                  FeatureNEON, FeatureRCPC, FeaturePerfMon,
                                  FeatureSPE, FeatureFullFP16, FeatureDotProd];

diff  --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt
index 3301680b1fd8d..8662b905a3f99 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt
@@ -1,6 +1,6 @@
 # RUN: llvm-mc -triple=aarch64 -mattr=+specrestrict -disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a        -disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s | FileCheck %s --check-prefix=NOSPECID
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple=aarch64 -mattr=-specrestrict -disassemble < %s | FileCheck %s --check-prefix=NOSPECID
 
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