[PATCH] D113890: [RISCV] Add new ELF attribute to track reserved registers

[Edward Jones via Phabricator via llvm-commits]

edward-jones added inline comments.


================
Comment at: llvm/include/llvm/MC/MCELFStreamer.h:95
     unsigned Tag;
-    unsigned IntValue;
+    uint64_t IntValue;
     std::string StringValue;
----------------
kito-cheng wrote:
> I would suggest change this into `APInt`, since we might also use more than 64 bits, e.g. vector register.
Okay, I suspect this will make things a bit more complicated since the setAttributeItem interface only accepts a fixed width value. I'll have to change it so that this attribute is emitted as a ULEB128.


================
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp:106
+  // attribute if it's non-empty.
+  uint64_t ReservedMask = 0;
+  for (unsigned Reg = 0; Reg < 32; Reg++) {
----------------
Something I needed to fix here. I believe the pull request mandates using the DWARF numbers for the registers and I need to do this in a more generic way here since right now the register numbers are just hardcoded in.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113890/new/

https://reviews.llvm.org/D113890