[PATCH] D120390: [RISCV] Add patterns for vector widening floating-point reduction instructions.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:1143
+defm : VPatWidenReductionVL<rvv_vecreduce_SEQ_FADD_vl, fpext_oneuse, "PseudoVFWREDOSUM", /*is_float*/1>;
+defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_SEQ_FADD_vl, riscv_fpextend_vl, "PseudoVFWREDOSUM", /*is_float*/1>;
+defm : VPatWidenReductionVL<rvv_vecreduce_FADD_vl, fpext_oneuse, "PseudoVFWREDUSUM", /*is_float*/1>;
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craig.topper wrote:
> Why do we check oneuse for fpext but not for riscv_fpextend_vl? Looks like we were inconsistent on this for integer too.
Done, I also change the integer pattern.


Repository:
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  https://reviews.llvm.org/D120390/new/

https://reviews.llvm.org/D120390